FIFO interrupt processing support

MasterPlayer / adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

MIT License

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FIFO interrupt processing support #57

Open MasterPlayer opened 1 year ago

MasterPlayer commented 1 year ago

There are needed for special processing for FIFO interrupts, because sw must read series of samples. Possible mechanism may be realized as next scheme: