search

MasterPlayer / adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
MIT License
3 stars 0 forks source link

testing in hw #6

Closed MasterPlayer closed 2 years ago

MasterPlayer commented 2 years ago

sometimes device go to state when no transactions in IIC bus, probably this problem in iic_bridge