problem with assignation register file

[MasterPlayer]

writing to register, when component await data might no effect

[MasterPlayer]

in register assignation we have next code :

            always @(posedge CLK) begin : register_proc
                if (~RESETN | reset)
                    register[reg_index] <= 0;
                else
                    if (slv_reg_wren) begin 
                        if (axi_dev_awaddr[ADDR_LSB_DEV+OPT_MEM_ADDR_BITS_DEV:ADDR_LSB_DEV] == reg_index) begin 
                            for ( byte_index = 0; byte_index <= (S_AXI_LITE_DEV_DATA_WIDTH/8)-1; byte_index = byte_index + 1 ) begin 
                                if ( S_AXI_LITE_DEV_WSTRB[byte_index] == 1 & write_mask_register[reg_index][byte_index]) begin 
                                    register[reg_index][byte_index] <= S_AXI_LITE_DEV_WDATA[(byte_index*8) +: 8];
                                end 
                            end 
                        end 
                    end else begin 
                        case (current_state) 
                            AWAIT_RECEIVE_DATA_ST : 
                                if (S_AXIS_TVALID) 
                                    if (address[5:2] == reg_index)  
                                        for ( byte_index = 0; byte_index <= 3; byte_index = byte_index + 1 ) begin
                                            if (byte_index == address[1:0])
                                                register[reg_index][byte_index] <= S_AXIS_TDATA;
                                        end 
                            default: 
                                register <= register;
                        endcase // current_state
                    end 

yes, writing is high priority and not accorded to fsm reading accorded to fsm

but next case:

1. FSM send request for reading data

2. FSM transit to state when await receive data

3. in this time, when request has been sended, and data not received, software perform writing to register, and enable need_update flaq

4. data received from device and save data to register

5. FSM goes to IDLE_ST

6. FSM sends request for writing data, but this data - such as data, readed from device (for example, when device POWER_CTL is x"00" value)

7. internal logic sends data with value x"00" to POWER_CTL_REG

[MasterPlayer]

solution : when reading from device and writing this values to device register file, need to analyze need_update flaq for this register for avoid rewriting data from device

[MasterPlayer]

Component updated to v.1.1

[MasterPlayer]

problem solved