I'm trying to adapt your project to work on a Sinclair QL (only the accelerator part).
There are some differences with the Amiga 500:
1) Sinclair QL uses a M68008 at 7,5MHz.
2) For the asynchronous bus control, the host interface (the ZX8301 ULA) manage the R/W, DTACK and DS signals (but not the AS signal).
3) VPA is self generated by the QL.
4) E and VMA are not controlled by the host interface.
I'd like to use these CPUs: M68008 at 10Mhz and a M68HC001 working in 8 bit mode (like the 68008) at 15MHz.
I'm trying to adapt your project to work on a Sinclair QL (only the accelerator part).
There are some differences with the Amiga 500: 1) Sinclair QL uses a M68008 at 7,5MHz. 2) For the asynchronous bus control, the host interface (the ZX8301 ULA) manage the R/W, DTACK and DS signals (but not the AS signal). 3) VPA is self generated by the QL. 4) E and VMA are not controlled by the host interface.
I'd like to use these CPUs: M68008 at 10Mhz and a M68HC001 working in 8 bit mode (like the 68008) at 15MHz.
Would you like to help me? Thank you.