Added RISC-V extension: IMC

[lavakrishna]

Reason for PR:

coresysservices-pf-example has build configurations

• miv-rv32i-debug (Base RV32I instruction set. Debug from RAM.)
• miv-rv32-imc-debug (Base RV32I instruction set + MC extension. Debug from RAM.)

Currently, miv-rv32i-debug build configuration can be run with CFG4 base design (PF_Eval_Kit_MIV_RV32_BaseDesign), But with miv-rv32-imc-debug can't be run with CFG4 base design (PF_Eval_Kit_MIV_RV32_BaseDesign).

Changed the design to support IMC RISC-V extension in CFG4 base design (PF_Eval_Kit_MIV_RV32_BaseDesign) with the help of GEN_DECODE_RV32.

• For CFG4 (PF_Eval_Kit_MIV_RV32_BaseDesign) added a clear explanation to the readme file

Evidence of test

Tested manually.

How to test:

Import the project coresysservices-pf-example into a soft console and follow the README file present in the example project.

[CLappin]

Hi @lavakrishna ,

Thank you for your pull request.

Please bare with us while we do a review.

Thanks, Ciaran