There are two configurations in the PolarFire-Eval-Kit repository that contain an issue with the two MIV_ESS Design Guide Configuration designs - DGC1 SPI-Boot and DGC3 uPROM-Boot. Specifically, the MIV_RV32's RESETN signal is improperly connected to the main central reset network instead of the MIV_ESS's reset controller signal (CPU_RESETN). This is affecting the overall functionality, preventing the soft-processor core from resetting after boot copy from external memory (SPI and uPROM) has completed.
Furthermore, the DGC3 design does not have the uPROM client flashed, leaving it empty.
To ensure the correct bootstrap sequence, it is necessary to connect the RESETN signal from MIV_RV32 to the CPU_RESETN signal on MIV_ESS for both DGC design configurations.
uPROM client in DGC3 needs to be flashed with example software provided.
CLappin
commented
1 year ago
There are two configurations in the
PolarFire-Eval-Kitrepository that contain an issue with the two MIV_ESS Design Guide Configuration designs - DGC1 SPI-Boot and DGC3 uPROM-Boot. Specifically, the MIV_RV32's RESETN signal is improperly connected to the main central reset network instead of the MIV_ESS's reset controller signal (CPU_RESETN). This is affecting the overall functionality, preventing the soft-processor core from resetting after boot copy from external memory (SPI and uPROM) has completed.Furthermore, the DGC3 design does not have the uPROM client flashed, leaving it empty.
The affected configurations are:
Resolution: