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MiSTeX-devel / MiSTeX-ports

FPGA board support and core ports for MiSTeX
BSD 3-Clause "New" or "Revised" License
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Fix digdug cpu clocks #12

Closed darfpga closed 8 months ago

darfpga commented 8 months ago

CLKS's original design don't compile correctly at least for Quartus 17.0 and for Max10. Don't understand why. CLKS[2] and CLKS[3] were 'merged'.

@hansfbaier : what's the best way to replace DIGDUG_CORES.v for MiSTeX ?

hansfbaier commented 8 months ago

Thanks!

darfpga commented 7 months ago

@hansfbaier : DigDug is now up to date on MiSTer repo with this fix. Can you please pull submodule to last commit ?

hansfbaier commented 7 months ago

@darfpga OK, done.

hansfbaier commented 7 months ago

@darfpga I can send you a MiSTeX baseboard for free, if you want. Are you interested? I am getting a run of 5 next week. https://github.com/MiSTeX-devel/MiSTeX-hardware/tree/main/QMTech-MiSTeX

QMTech-MiSTeX Baseboard

darfpga commented 7 months ago

@hansfbaier

Hello Hans, thank you very much for the offer. I'am going to think about it. I have so little time to spend on this hobby (unfortunately).