Create terasic_de10lite_mistex.py

MiSTeX-devel / MiSTeX-ports

FPGA board support and core ports for MiSTeX

BSD 3-Clause "New" or "Revised" License

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Closed darfpga closed 11 months ago

darfpga commented 11 months ago

MiSTeX DE10_lite to RPI zero interface

Quartus conversion command : quartus_cpf.exe -c -q 24.0MHz -g 3.3 -n p .sof .svf

MiSTer.ini MiSTeX configuration variables : bitstream_extension=.svf fpgaloader_cmd=openFPGALoader -b de10lite

hansfbaier commented 11 months ago

@darfpga Hi, thanks for the contribution! Just one thing: Can you remove the commented out lines of the hardware that is unused? Thanks!

hansfbaier commented 11 months ago

OK, that looks good. Thanks!