Closed jopdorp closed 2 years ago
Your code of NE555 is very complex and gives big slack (-19ns). It's better to rewrite it (and probably filters too) to make it more FPGA friendly. For example multiply and divide are very resource hungry operations and should be minimized/eliminated as much as possible. Also complex math may need longer time than one clock cycle used in module. So it needs to be spread across several cycles (i.e use pipeline).
Your code of NE555 is very complex and gives big slack (-19ns). It's better to rewrite it (and probably filters too) to make it more FPGA friendly. For example multiply and divide are very resource hungry operations and should be minimized/eliminated as much as possible. Also complex math may need longer time than one clock cycle used in module. So it needs to be spread across several cycles (i.e use pipeline).
Thanks for the feedback.
I was reaching out for help what to do with this yesterday on the the discord, and had a call with spacexguy about it. My current plan is to add a multicycle path for the division in the 555 timer, see if I can get rid of the -19 slack like that.
I don't think it's possible to get rid of all divisions in discrete simulation, but I do plan to do iterative improvements of the individual modules in the MiSTer Discrete system.
This way as the projects evolve, earlier implementations like this one will improve too.
One of the first things on my list are the filters.
Actually audio 3-tap IIR filter is already implemented in sys folder. It can be used for both HPF and LPF with minimum resources. I've implemented it specifically for general use in cores.
improved based on feedback on the last version: