possibility to use the SDRAM for cartram, too - the full 18 bit address space is usable (not added to the toplevel, as I cannot test it without a de10-nano)
use tRCD=2 cycles, but don't register the SDRAM output twice - same data delay, but obey the datasheet
I only compile-tested these with the MiSTer target, but they're working well on MiST. The cartram move to SDRAM needs a simple address multiplexer in the toplevel, like this: https://github.com/gyurco/Atari7800_FPGA/blob/4e0a8cd9a3cdc37945e89921d5166fd91a6ca098/mist/Atari7800_MiST.sv#L658