search

MiSTer-devel / Chess_MiSTer

7 stars 2 forks source link

UCI feature ? #2

Open bhamadicharef opened 4 years ago

bhamadicharef commented 4 years ago

Any plans to add a UCI ? https://en.wikipedia.org/wiki/Universal_Chess_Interface

Brahim

RobertPeip commented 4 years ago

It would be a nice feature. However, there are no easy ways to communicate between Mister core internals and a PC, e.g. over ethernet, that i know of.

If the Mister had a serial port (e.g. USB via FTDI) connected to FPGA fabric, i would do it, but it only has such a thing for the HPS/ARM.

If we ever get an easy path for direct Core<->PC communication that works for everyone, i would add it, just to compare against existing engines :)

sorgelig commented 4 years ago

well, serial interface can be output through user_io port

bhamadicharef commented 4 years ago

Yes Robert ... to compare against existing engines :) ... Nice work ! a Simple UART using the user_io port would be nice. Not sure if someone implemented the UCI engine in HDL ... google will tell us !

RobertPeip commented 4 years ago

UART over Pins with some external FTDI board would work, but would you really use it?

For comparing against existing engines: i have the same AI logic implemented also in Javascript and C#, which you can find in my Github projects. While the FPGA solution is faster (mainly because the .js/.cs are single core and not optimized at all), the quality is the same.