MiSTer-devel / EDSAC_MiSTer

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
MIT License
11 stars 2 forks source link

rename edsac.sv to EDSAC.sv #5

Closed birdybro closed 4 months ago

birdybro commented 3 years ago

Finally fixes the flaw with the script I had tried to fix earlier (renaming to caps has to be done differently than just pushing to github apparently, the pushes are not case-sensitive).