Can't open project -- Quartus Prime (v17) Settings File contains one or more errors

[Phi-Ho]

Greetings,

Thank you for releasing Conway's Life to remember his life.

Quartus Prime (v17) could not load the project:

Error (125048): Error reading Quartus Prime Settings File G:/FPGA/DE10/MisterFPGA/Cores/Life_MiSTer/Life.qsf, line 41 Info (125063): set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON

Warning (125092): Tcl Script File video_pll.qip not found Info (125063): set_global_assignment -name QIP_FILE video_pll.qip Warning (125092): Tcl Script File video_pll.sip not found Info (125063): set_global_assignment -name SIP_FILE video_pll.sip

Please advise if Quartus 16.1.2 is required and video_pll.qip is not needed.

Best regards,

phiho

[hrvach]

Please check the Quartus version used to create the file - I used what I had available at the time, and apparently issues of cross-version compatibility are becoming painfully obvious :(

[Phi-Ho]

Greetings,

Actually, I tried v16 and got the same errors.

It is interesting that Quartus 20.1.1 loaded the project OK but there is an error in the source:

Info: *** Info: Running Quartus Prime Shell Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Processing started: Thu Dec 17 23:29:33 2020 Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Processing started: Thu Dec 17 23:29:33 2020 ... ... ... Error (10170): Verilog HDL syntax error at Life.sv(163) near text: ")"; mismatched closing parenthesis . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at Life.sv(163) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "emu" at Life.sv(8) due to previous errors

This was fixed: // output_pixel <= status[3] ? r2p2 : (neighbor_count | r2p2) == 4'd3) || ((neighbor_count ^ r2p2) == 4'd6; output_pixel <= status[3] ? r2p2 : ((neighbor_count | r2p2) == 4'd3 || (neighbor_count ^ r2p2) == 4'd6);

and the build was successful (with warnings).

BTW, in the menu, there are the options to turn on "High Life" and "Seed", what do these options do.

Regards,

phiho

[sorgelig]

Standard Quartus version for MiSTer is 17.0.x I urge developers to fix their project to be able to use 17.0.x Later Quartus version gives absolutely nothing. They only mess the settings making it incompatible. Ne new features in newer Quartus.

[Phi-Ho]

Dear All,

Happy New Year to you and your family.

Best regards,

phiho

[birdybro]

@Phi-Ho - this should be fixed in this PR --> https://github.com/MiSTer-devel/Life_MiSTer/pull/5