this would make the core pretty much perfect feature wise :) Any plans to implement OPL4 support at some point?
It appears that OPL4 is "too large" for the FPGA used in OCM (12000 LEs). MiSTer on the orher hand, has 110000 LEs, so there would be plenty of space at least to my understanding.
Hi,
this would make the core pretty much perfect feature wise :) Any plans to implement OPL4 support at some point?
It appears that OPL4 is "too large" for the FPGA used in OCM (12000 LEs). MiSTer on the orher hand, has 110000 LEs, so there would be plenty of space at least to my understanding.
Ther's an OPL4 design made with C here:
https://github.com/vgmrips/vgmplay/blob ... ymf278b.c
To my understanding it could be converted to VHDL/Verilog, but I could be terribly wrong (also) here.