Remove logic ramstyle attributes from vm2413

[birdybro]

These were originally added for the SMS core by gyurco to help the core fit on MiST's Cyclone III chip which has significantly less BRAM. I kept the module registermemory.vhd asserted into logic as this actually caused timing issues for it the ramstyle to be removed (it asserts into M10k when left to automatically infer, which is slower than logic in most cases). The other 3 modules changed inferred to MLAB automatically, which is somewhat faster than logic usually.

ALMS reduced from 34,003 to 33,834. Registers used reduced from 52178 to 51469. RAM blocks used increased from 438 to 442 (out of 553 total). No significant timing analysis differences were observed as a result of this change.

[sorgelig]

I think those arrays are very shallow and will waste BRAM. ALMS/Register usage is "breathing" from build to build. Numbers you shown aren't exactly showing decrease due to your changes. Next build with even small change may increase (or decrease) usage randomly.

[birdybro]

Thanks for reviewing the change. Your explanation makes sense.