There are some places in Minimig code where continuous assignments are being used for registers. It seems this doesn't make any difference for synthesis. But when simulating in verilator, the results will not run as those assignments don't match the timing of other ones.
These patches make the code run in verilator but don't break synthesis ... at least not for gowin FPGAs
In beamcounter parts of an array are used within a register while bit0 uses a continuous assignment. Verilator doesn't like that. The following patch ads a variant that verilator likes:
There are some places in Minimig code where continuous assignments are being used for registers. It seems this doesn't make any difference for synthesis. But when simulating in verilator, the results will not run as those assignments don't match the timing of other ones.
See e.g. these patches: https://github.com/harbaum/NanoMig/commit/22979a96d9cc6bbd8233a52b4384a550cf5d71a1 and https://github.com/harbaum/NanoMig/commit/0df4bd0d87b30c3ceecb47e0cbd7d846182a9b6d
These patches make the code run in verilator but don't break synthesis ... at least not for gowin FPGAs
In beamcounter parts of an array are used within a register while bit0 uses a continuous assignment. Verilator doesn't like that. The following patch ads a variant that verilator likes:
https://github.com/harbaum/NanoMig/commit/d8d1b9d4d3b4cef78f928d7e354e491150f14001
As a result the code can be run in verilator making things like this possible:
https://github.com/harbaum/NanoMig/tree/main/sim