RTG from FPGAArcade?

[apolkosnik]

Not really an issue, but I wanted to start a conversation about what it would take to get the RTG from FPGAArcade integrated into MiSTer.

[apolkosnik]

For the first step, I've rolled the files into the build (at least Quartus is not complaining anymore, and it builds). Also it's depending on M68K being enabled and the RAM_LUT that was reimplemented for M68K in MiSTer.

https://github.com/apolkosnik/Minimig-AGA_MiSTer/tree/rtg

Looking at the VDE/VBE comments it needs some stuff:

-- Extended clock modes
-- 40.0 MHz, 50.0MHz, 74.25MHz plus sys clock and /n
--

-- i_clk is the sysem clock, base clock * 4 ~= 28MHz
-- i_ena is a one in four clock enable
-- i_cph is a four phase enable. i_cph(3) == i_ena
--     __              __              __
--  __/  \____________/  \____________/  \__                 i_ena
--
--    <P3><P0><P1><P2><P3><P0><P1><P2><P3>                   i_cph

[sorgelig]

Actually HDL part can be simplified for MiSTer. Scaler supports rendering from frame buffer, so i wanted to re-use the frame buffer mode for RTG. In this case Minimig doesn't need to switch between video outputs but just continue to provide AGA video while RTG drivers will use DDR3 memory for RTG video. The problem is that i'm not familiar with RTG on Amiga. I never had RTG in my Amiga. I don't know how RTG/AGA switching is handled. I believe in most cases RTG has separate video output so it's up to the user when to switch his monitor between RTG and AGA manually. But i think there should be some automatic way to switch - probably coming from RTG driver. So if there is such flag, then we can use.

i_clk is 28MHz (clk_sys) i_ena - it can be clk7_en or clk7n_en - depending on required phase. i_cph - should be manually created from i_ena

[apolkosnik]

Most RTG implementations use separate connector, however, a recently released ZZ9000 (FPGA based) actually features a scandoubler and flicker-fixer that handles native video and RTG via the single connector. Best of all, the sources are available here: https://source.mntmn.com/MNT I guess that the P96 does the switching once the RTG is activated, and the following function gets called to do what's needed: https://source.mntmn.com/MNT/zz9000-drivers/src/branch/master/rtg/mntgfx.c#L548

The bonus is an on-board network card.

[sorgelig]

Source for ZZ9000 are only for drivers. I don't see HDL sources

[sorgelig]

Btw, i have no plans to work on RTG in foreseeing future. But if you or someone else will add initial port/implementation, i can add improvements on HDL side.

[apolkosnik]

The code that drives the fpga is here: https://source.mntmn.com/MNT/zz9000-firmware

[sorgelig]

i see. It seems pretty complex as it uses hybrid ARM/FPGA system. Although i didn't check precisely if ARM is used for RTG part.

[alynna]

I will look into this in a soonish manner because I am working on a simple framebuffer for my own project and I do want to see RTG. Probably after the christmas season (dev is going slow right now)

[limi]

There’s RTG support in the core now (added by Grabulosaure), so I believe this issue can be closed.