MCLZ8 - Faulty IR with DDCBnn46 (BIT 0, (IX+nn)) - Githubissues

MicroCoreLabs / Projects

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8

372 stars 78 forks source link

MCLZ8 - Faulty IR with DDCBnn46 (BIT 0, (IX+nn)) #21

Open hlide opened 1 year ago

hlide commented 1 year ago

nn shall not be a fetched opcode (no /M1 = 0 and R shall not increase).

MicroCoreLabs commented 10 months ago

I will make this change. Thanks for pointing this out!

Thx -Ted

From: hlide @.> Sent: Monday, July 17, 2023 6:11 PM To: MicroCoreLabs/Projects @.> Cc: Subscribed @.***> Subject: [MicroCoreLabs/Projects] MCLZ8 - Faulty IR with DDCBnn46 (BIT 0, (IX+nn)) (Issue #21)

nn shall not be a fetched opcode (no /M1 = 0 and R shall not increase).

[image]https://user-images.githubusercontent.com/56785/254106763-039ea794-f54a-45ec-b465-9800cf3a9642.png

— Reply to this email directly, view it on GitHubhttps://github.com/MicroCoreLabs/Projects/issues/21, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AM4AVENMQH32WHJZ4S5TPWDXQXPDBANCNFSM6AAAAAA2NVJLBY. You are receiving this because you are subscribed to this thread.Message ID: @.***>