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MicroCoreLabs / Projects

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8
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Wheelwriter project, errors synthesizing #23

Open johnwiggins opened 10 months ago

johnwiggins commented 10 months ago

I get an error trying to synthesize mclwr1.v in Diamond 3.6 or 3.12:

documents/impl1/source/mclwr1.v(120): net rx_fifo_wr is constantly driven from multiple places at instance RX_FIFO, on port WrEn. VDB-1000 Done: error code 2

And programming directly from the JEDEC in the repo produces transmit checksum errors and results in a non-functional board.

MicroCoreLabs commented 10 months ago

Did you create FIFO cores using the Lattice IP tool?

johnwiggins commented 10 months ago

Ouch, I did not. Sorry, newb here.

In the IPexpress tool, it looks like FIFO_DC is available for the XO2, but not FIFO. Is that sufficient?

Creating FIFO_DC (1024 depth) and including them in the synthesis cleared the error.