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Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8
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Bug in RISCV_C_Version? #4

Open michaelengel opened 4 years ago

michaelengel commented 4 years ago

The comparison operator for "BLTU" in riscv.c (l. 91) should be "<" instead of ">=" (this line is identical to the "BGE" line below it except for the instruction name):

if (opcode==0b1100011 && funct3==0b110) { if (rv5_reg[rs1]>=rv5_reg[rs2]) rv5_pc = ( (B_immediate_SE) + rv5_pc) - 0x4; printf(" BLTU "); } else // BLTU

MicroCoreLabs commented 4 years ago

Fixed!

Thanks, -Ted

From: Michael Engel notifications@github.com Sent: Friday, April 3, 2020 1:31 PM To: MicroCoreLabs/Projects Projects@noreply.github.com Cc: Subscribed subscribed@noreply.github.com Subject: [MicroCoreLabs/Projects] Bug in RISCV_C_Version? (#4)

The comparison operator for "BLTU" in riscv.c (l. 91) should be "<" instead of ">=" (this line is identical to the "BGE" line below it except for the instruction name):

if (opcode==0b1100011 && funct3==0b110) { if (rv5_reg[rs1]>=rv5_reg[rs2]) rv5_pc = ( (B_immediate_SE) + rv5_pc) - 0x4; printf(" BLTU "); } else // BLTU

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHubhttps://github.com/MicroCoreLabs/Projects/issues/4, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AM4AVEP4WO5ODXIB3TLU7FTRKZBSDANCNFSM4L4NRKQQ.

michaelengel commented 4 years ago

Sure, you're welcome! Very nice compact code - I wrote a RISC V emulator for my students in Go, this took quite a number of lines more...

Oh, and thanks for open sourcing your CPU cores, very much appreciated!

Best, Michael

On 3 Apr 2020, at 23:40, MicroCoreLabs notifications@github.com wrote:

Fixed!

Thanks, -Ted

From: Michael Engel notifications@github.com Sent: Friday, April 3, 2020 1:31 PM To: MicroCoreLabs/Projects Projects@noreply.github.com Cc: Subscribed subscribed@noreply.github.com Subject: [MicroCoreLabs/Projects] Bug in RISCV_C_Version? (#4)

The comparison operator for "BLTU" in riscv.c (l. 91) should be "<" instead of ">=" (this line is identical to the "BGE" line below it except for the instruction name):

if (opcode==0b1100011 && funct3==0b110) { if (rv5_reg[rs1]>=rv5_reg[rs2]) rv5_pc = ( (B_immediate_SE) + rv5_pc) - 0x4; printf(" BLTU "); } else // BLTU

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHubhttps://github.com/MicroCoreLabs/Projects/issues/4, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AM4AVEP4WO5ODXIB3TLU7FTRKZBSDANCNFSM4L4NRKQQ. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub, or unsubscribe.