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MicroCoreLabs / Projects

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8, MCL6809, XTMax
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Add dynamic mode change by writing to $d030 #8

Open icepic opened 3 years ago

icepic commented 3 years ago

Only compile tested, I have no teensy4.1 MCL kit yet.

Lots of later improvements possible, like checking where screen ram actually is runtime and so on, but this should be no change from the compile-time SPEEDUP value used before, but allows code to set other values at runtime.

icepic commented 3 years ago

Hopefully current_p was the item that keeps track of addr 1 mapping changes.

Also, found a small nit that would make writes to 0x02 behave different from 0003->ffff. I think only addr 0 and 1 are special, 0x2 is commonly used as the first free zp memory location so it should act like 3,4,5,6 and so on.

ytmytm commented 3 years ago

I think only addr 0 and 1 are special, 0x2 is commonly used as the first free zp memory location so it should act like 3,4,5,6 and so on.

Yes, 0x02 is plain RAM.

The address 0x00 is the CPU port direction register and 0x01 the port data register.

Interestingly, these two don't really belong to RAM - writing to these two addresses doesn't drive external control lines on 6510 (section 4 of https://www.cebix.net/VIC-Article.txt ), but I don't believe handling this special case would make any difference regarding compatibility. The only way to read/write RAM at 0x00/0x01 is to trick VIC into doing it for you. That's a lot of extra effort not needed in games or demos.