Open picerno76 opened 1 year ago
The fix above partially resolves the issue. Since the drv_i2s doesn't use chained channels, in the DMA interrupt we don't have much time to start the channels again. In my case few code in the client callback made me late to start the DMA transfers in good time. Moving the call of the client callback after the DMA transfers seems the best solution. What do you think of this new fix? Could there be other negative effects? drv_i2s.txt
If you call DRV_CODEC_BufferAddWriteRead, the receive buffer is missing the first sample so if you pass it to the next transmit buffer you have inverted channels. This is my fix drv_i2s.txt
I spent time to find out it because there is a configuration issue in the I2S PLIB regarding SPI2_CON_FRMPOL. It is always configured to 1. In left justified mode is OK but in I2S mode, it works well for me at 0.
I would appreciate if you add also specific cache code for PIC32 like that for E70