in mrpc dma mode, dma target address register with offset
0x810-0x817 and mrpc dma mode enable register with offset 0x80c in
gas space
driver set the dma target address register first, then
enable mrpc dma mode following, but because mrpc section with WC
attribute, these 2 writes were combined and resulting enable dma
first then followed by the dma target address, that's 3 dwords write
from 0x80c to 0x817, add the necessory barrier between
the memory barrier also added when disable mrpc dma
in mrpc dma mode, dma target address register with offset 0x810-0x817 and mrpc dma mode enable register with offset 0x80c in gas space driver set the dma target address register first, then enable mrpc dma mode following, but because mrpc section with WC attribute, these 2 writes were combined and resulting enable dma first then followed by the dma target address, that's 3 dwords write from 0x80c to 0x817, add the necessory barrier between
the memory barrier also added when disable mrpc dma