Closed RRozak closed 12 months ago
It is how these parameters are defined: https://github.com/antmicro/uvm-verilator/blob/eb0cef0c4154386381196ec0142ed876bfc2ed1b/src/seq/uvm_sequencer.svh#L34 If you pass a value only to the first one, the 2nd should have the same value assigned. But it doesn't work yet in Verilator, so always values for both parameters should be passed.
It adds a workaround for the problem with
uvm_sequncer
: https://github.com/verilator/verilator/issues/4497. The 2nd parameter is optional and is equal to the 1st by default. Verilator doesn't handle it correctly, so always 2 parameters should be provided.