Runtime error: `%Error: ../rtl/../tb/top.sv:20: Input combinational region did not converge.`

[infinitymdm]

Summary

When attempting to run the run_verilator.sh script with ./run_verilator testname, verilation completes but a runtime error is produced when attempting to run the file. The full verilation output is in the attached logfile. Just the runtime error is displayed below.

marcus@fiora ~/software/GettingVerilatorStartedWithUVM/scripts $ ./run_verilator.sh testname #After previously verilating
Using /home/marcus/software/cu-fpga/include/uvm-verilator/src/ to point at your UVM class library
make: Entering directory '/home/marcus/software/GettingVerilatorStartedWithUVM/scripts/verilator_obj_dir'
make: Nothing to be done for 'default'.
make: Leaving directory '/home/marcus/software/GettingVerilatorStartedWithUVM/scripts/verilator_obj_dir'
- V e r i l a t i o n   R e p o r t: Verilator 5.029 devel rev v5.028-70-g4a589976
- Verilator: Built from 0.000 MB sources in 0 modules, into 0.000 MB in 0 C++ files needing 0.000 MB
- Verilator: Walltime 2.203 s (elab=0.000, cvt=0.000, bld=2.174); cpu 0.030 s on 48 threads; alloced 8.574 MB
UVM_INFO @ 0: reporter [UVM/RELNOTES] 
  ***********       IMPORTANT RELEASE NOTES         ************

  This implementation of the UVM Library deviates from the 1800.2-2017
  standard.  See the DEVIATIONS.md file contained in the release
  for more details.

----------------------------------------------------------------
Accellera:1800.2-2017:UVM:1.0

All copyright owners for this kit are listed in NOTICE.txt
All Rights Reserved Worldwide
----------------------------------------------------------------

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO @ 0: reporter [RNTST] Running test data0_test...
%Error: ../rtl/../tb/top.sv:20: Input combinational region did not converge.
Aborting...
./run_verilator.sh: line 149: 139416 Aborted                 (core dumped) ./verilator_obj_dir/Vuvm_pkg +UVM_TESTNAME=data0_test

full_verilation_log.txt

Software Configuration

Verilator: https://github.com/verilator/verilator/commit/4a589976041a4157c89b642d4757c3b99f32c5b4

marcus@fiora ~/software/GettingVerilatorStartedWithUVM/scripts $ verilator --version
Verilator 5.029 devel rev v5.028-70-g4a589976

UVM Library: https://github.com/antmicro/uvm-verilator/commit/2e667ac506c12e91d81bde62fe2c08d992731bd4

marcus@fiora ~/software/cu-fpga/include/uvm-verilator/src $ git log --oneline -n1
2e667ac (HEAD -> current-patches, antmicro/current-patches) Remove rand specifier in dynamic arrays and queues

I also made a couple slight tweaks to the script (reduce error spam in UVM library, use all cores for verilation)

marcus@fiora ~/software/GettingVerilatorStartedWithUVM/scripts $ git diff
diff --git a/scripts/run_verilator.sh b/scripts/run_verilator.sh
index 42975cf..c82e36c 100755
--- a/scripts/run_verilator.sh
+++ b/scripts/run_verilator.sh
@@ -116,7 +116,8 @@ DISABLED_WARNINGS="-Wno-DECLFILENAME \
                    -Wno-ZERODLY \
                    -Wno-SYMRSVDWORD \
                    -Wno-CASEINCOMPLETE \
-                   -Wno-REALCVT"
+                   -Wno-REALCVT \
+                   -Wno-SIDEEFFECT"

 # compile
  verilator \
@@ -128,7 +129,7 @@ DISABLED_WARNINGS="-Wno-DECLFILENAME \
      --error-limit 5 \
      --binary \
      --hierarchical \
-     -j 1 \
+     -j `nproc` \
      -Wall \
      $DISABLED_WARNINGS \
      +define+UVM_REPORT_DISABLE_FILE_LINE \

I've been trying to get my own UVM testbenches to work with verilator, and have run into the same runtime error there. Thought I'd give yours a try, but no luck apparently. Are you experiencing the same error?

[MikeCovrado]

Hi @infinitymdm, thanks for your interest. As per the README, I have not yet been able to get this environment to compile with Verilator:

Last tested with Verilator v5.018 on Ubuntu 22.04.
Not yet compiling (working on it).

I appreciate you giving it a try with v5.029.

As far as I am aware, Verilator cannot yet handle UVM, even using uvm-verilator from Antmicro. Note that the UVM environment in this repo has been cut down to create what I consider to be the basic-of-the-most-basic example of a "complete" UVM environment.

I am encouraged by the success you had compiling the environment (the errors are all run-time, not compile-time, which is an improvement over v5.018). Verilator is getting closer, but is not there yet.