MikePopoloski / slang

SystemVerilog compiler and language services
MIT License
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[bug][slang] Incorrect empty ports. #1017

Closed Kitaev2003 closed 3 weeks ago

Kitaev2003 commented 3 weeks ago

Describe the bug Hello, is this code correct? If so, maybe you should add diagnostics for this code or mark these ports as invalid?

To Reproduce


module top( , , );

endmodule
{
"name": "top",
"kind": "Instance",
"addr": 2199025898640,
"body": {
    "name": "top",
    "kind": "InstanceBody",
    "addr": 2199025898352,
    "members": [
    {
        "name": "",
        "kind": "Port",
        "addr": 2199025898784,
        "type": "void",
        "direction": "In"
    },
    {
        "name": "",
        "kind": "Port",
        "addr": 2199025898960,
        "type": "void",
        "direction": "In"
    },
    {
        "name": "",
        "kind": "Port",
        "addr": 2199025899136,
        "type": "void",
        "direction": "In"
    }
    ],
    "definition": "2199025942528 top"
},
"connections": [
]
}
MikePopoloski commented 3 weeks ago

Yes, the code is valid. There is an isNullPort member that is not included in the JSON serialization but easily could be.

MikePopoloski commented 3 weeks ago

Added in ad5cda219803a4829c70a2e4bea24d04591a32c3