Error occurs when instantiating submodule and passing parameters without using parentheses

Describe the bug The submodule has only one parameter, and when the upper layer instantiates the submodule, it uses: submaodule #value instname (...) to assign values to the submodule parameter, resulting in a compilation error even if with --compat vcs argument.

To Reproduce

module a (i0, i1, o1);
parameter B_SIZE = 8;
input [B_SIZE-1:0] i0;
input [B_SIZE-1:0] i1;
output [B_SIZE-1:0] o1;

assign o1[B_SIZE-1:0] = i0[B_SIZE-1:0] + i1[B_SIZE-1:0];
endmodule

module b(i0, i1, o1);
input [65:0] i0;
input [65:0] i1;
output [65:0] o1;

a #66 new_adder(.i0 (i0 ), .i1(i1 ), .o1(o1 ));

endmodule

Additional context The offcial definition of the syntax for module instantiation has parentheses in parameter value assignment, but vcs supports the instantiation above.

MikePopoloski / slang

Error occurs when instantiating submodule and passing parameters without using parentheses #868