MikePopoloski / slang

SystemVerilog compiler and language services
MIT License
550 stars 117 forks source link

Module resolution in libraries #906

Closed Krym4s closed 2 months ago

Krym4s commented 2 months ago

If several files have modules with similar names, slang cannot distinguish it and inline it in elaborated model. This problem is related to 33.6 chapter of LRM.

Example:

// file top.v
config cfg1;
design top;
default liblist aLib gateLib;
endconfig

module top();
logic a;
adder a1(a);
adder a2();
endmodule

//file adder.v

module adder(logic a);
endmodule;

//file adder.vg

module adder();
endmodule;

//file lib.map
library aLib adder.v;
library gateLib adder.vg;
slang top.v --libmap=lib.map

Module top in code above should find module adder in library aLib and different module adder in gateLib. Slang finds both module definition, but have problem with building elaborated model and throws an error.

MikePopoloski commented 2 months ago

Are you using master or the 5.0 release? Support for configurations was added after 5.0 was released.

Krym4s commented 2 months ago

Hello, we run this example on the master branch.

Krym4s commented 2 months ago

Code example was slightly changed.

MikePopoloski commented 2 months ago

You need to tell slang to use the configuration, so something like slang top.v --libmap=lib.map --top cfg

Krym4s commented 2 months ago

Thank you, everything is working now.