MikePopoloski / slang

SystemVerilog compiler and language services
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$assertoff() gets errors when passed a module hierarchy for recursive assertion disabling #907

Closed jrudess closed 2 months ago

jrudess commented 2 months ago

From the LRM, the 2nd argument allows a 'scope_or_assertion' which is a 'hierarchical_identifier'. So I believe that passing a module hierarchy to the 2nd argument should be allowed here. The original code is attempting to disable all assertions recursively within a module-hierarchy.

slangtest155.sv:18:23: error: expected scope or assertion name
        $assertoff(0, m);
                      ^
module M(
    input logic clk,
    input logic rst_b
);
    myprop: assert property(@(posedge clk) disable iff (rst_b) ~1);
endmodule

module top;
    logic clk;
    logic rst_b;

    M m(
        .clk   (clk),
        .rst_b (rst_b)
    );

    initial begin
        $assertoff(0, m);
        $assertoff(0, m.myprop);
    end
endmodule
MikePopoloski commented 2 months ago

Fixed in 01eb6f6a0a14800983fb18787f57df6029de87dd