Describe the bug
The following code is not allowed by slang:
`define D #1
module x;
reg a;
wire clk;
always_ff @(posedge clk)
a <= `D 1'b0;
endmodule
To Reproduce
Run the code above.
Additional context
The LRM says:
_The always_ff procedure imposes the restriction that it contains one and only one event control and no
blocking timing controls. Variables on the left-hand side of assignments within an alwaysff procedure,
including variables from the contents of a called function, shall not be written to by any other process.
I think the term blocking timing controls is ill-defined (I couldn't find any definition in the spec of blocking vs non-blocking in the context of delays), but I don't think it includes the case above, which is typical for synthesizable code where you want such delays to make the output more clear.
The 2 simulators I tested happily accept this code.
Describe the bug The following code is not allowed by slang:
To Reproduce Run the code above.
Additional context The LRM says:
_The always_ff procedure imposes the restriction that it contains one and only one event control and no blocking timing controls. Variables on the left-hand side of assignments within an alwaysff procedure, including variables from the contents of a called function, shall not be written to by any other process.
I think the term blocking timing controls is ill-defined (I couldn't find any definition in the spec of blocking vs non-blocking in the context of delays), but I don't think it includes the case above, which is typical for synthesizable code where you want such delays to make the output more clear. The 2 simulators I tested happily accept this code.