MikePopoloski / slang

SystemVerilog compiler and language services
MIT License
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Add a global check for overlapping net aliases #947

Open MikePopoloski opened 1 month ago

MikePopoloski commented 1 month ago
To avoid errors in specification, it is not allowed to specify an alias from an individual signal to itself or to
specify a given alias more than once. The following version of the preceding code would be illegal because
the top 4 bits and bottom 4 bits are the same in both statements:
  alias bus16 = {high12[11:8], low12};
  alias bus16 = {high12, low12[3:0]};

This alternative is also illegal because the bits of bus16 are being aliased to itself:
  alias bus16 = {high12, bus16[3:0]} = {bus16[15:12], low12};