Excuse me, sir. When I tested the vector bit-select and part-select operations in slang v3.0, I found their results were not as described.
Example: (Please see IEEE 1800-2017 § 11.8.1 "Rules for expression types".)
.sv
module Foo;
logic [15:0] a;
logic signed [7:0] b;
initial
a = b[7:0];
endmodule
Excuse me, sir. When I tested the vector bit-select and part-select operations in slang v3.0, I found their results were not as described. Example: (Please see IEEE 1800-2017 § 11.8.1 "Rules for expression types".)
.sv
.json