Function name used as variable causes error in VCS compatibility mode

[hankhsu1996]

Describe the bug In compatibility mode with VCS, using the slang compiler throws an error when a function name is used as a variable within the function's own scope. This behavior differs from VCS, where no error is thrown.

To Reproduce Steps to reproduce the behavior:

1. Create a SystemVerilog file test.sv with the following content:

   module my_mod;
   function automatic logic my_func();
   my_func = 1'b1;
   assert (my_func === 1'b1)
     else $error("Expect my_func to return 1 but got %0b", my_func);
   endfunction
   endmodule

2. Compile the file using slang in VCS compatibility mode with the command:

   slang test.sv --compat vcs

3. Observe the following error:

   error: parentheses are required when invoking function 'my_func'
     else $error("Expect my_func to return 1 but got %0b", my_func);
                                                           ^~~~~~~

Additional context In normal mode (without --compat vcs), it can pass without error.

[MikePopoloski]

Fixed in 42dfd0ca3be747ea5e85c8e33e0a3d8f7591776e