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MinecraftMachina / FabricHDL

A Verilog synthesis flow for Minecraft redstone circuits
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Same track channel skips repeater, causing redstone signal decay #1

Open ViRb3 opened 2 years ago

ViRb3 commented 2 years ago

In general, when the code tries to connect two tracks, the channel will be at least 3 blocks wide, and a repeater will be placed in the middle to extend the redstone signal. However, there appears to be a case when the code tries to connect the same track to itself, which results in a 1-width block and no repeater. This can cause the redstone signal to decay and not reach further down the circuit.

Best visualized below:

Screen Shot 2022-03-13 at 23 59 06

ViRb3 commented 2 years ago

Upstream issue: https://github.com/itsFrank/MinecraftHDL/issues/14