Perform sanity checks for Verilog-style literals

Minres / CoreDSL

Xtext project to parse CoreDSL files

Apache License 2.0

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Perform sanity checks for Verilog-style literals #14

Closed jopperm closed 2 years ago

jopperm commented 2 years ago

5'd42 should trigger an error (doesn't fit) 6'sd42 should trigger a warning (does fit, but the represented decimal value is -22, which might be unexpected)

jopperm commented 2 years ago

Updated spec in https://github.com/Minres/CoreDSL/wiki/_compare/436e45fd0f43e642b52812ea223ecf5104759920 and https://github.com/Minres/CoreDSL/wiki/_compare/5808aeb75dc99eaadd282f6fcce259c82cf7d13e...ec8270b48092ae6196db0c474962508bb283cab8.