Minres / RISCV_ISA_CoreDSL

CoreDSL descriptions of the RISC-V ISA
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Floating Point Instructions should raise Illegal Instruction Exception #1

Open fpedd opened 2 years ago

fpedd commented 2 years ago

When the Extension Context Status field for the floating-point extension (FS[1:0], bits 14:13 in mstatus) is set to Off an illegal instruction exception should be raised (see privileged spec section 3.1.6.6).

As far as I can see this is not currently checked by the CoreDSL. The only solution I see is that one would need to check the mstatus field in every floating-point instruction (likely using the functions feature offered by CoreDSL 2). This appears very verbose. Maybe there are more elegant solutions to this.

The application would then need to enable the floating-point extension by writing a 1 into the FS[1:0] field before executing any floating-point instructions. This can, for example, be accomplished by:

li t0, 1<<13
csrs mstatus, t0

The same holds true for the vector extension (or any other extension that has an Extension Context Status field in mstatus).