Closed PhilippvK closed 5 months ago
@eyck Could you please have a look. I just learned that name(…)
should make use of the aliases defined for the individual (GPR) registers. If that is the case I could rename fname
to name
and add the proper aliases for the 32 Float Regs instead.
Actually there is no specification of the asm format stirng set. So this is free form (a bit inspired by Python f strings) and since fstrings allow to call functions within the braces I introduced the name() function to look up the ABI names of the GPRs from register numbers. Are there aliases for the AF registers? If so we can keep the fname() in the format string otherwise it is totally legal (and it was orignally this way) to write "f{rd}, f{rs1}, f{rs2}"
which is supposed to result in something like f3, f7, f9
The RISC-V calling convection defines names for the F0-F31 registers, thus we should probably use/implement them.
I see, so we should keep the fname() function for the format strings. Maybe we should rename them to gpr_name and fp_name?
@wysiwyng WDYT?
@eyck I think we should finally get this merged...
I saw that there is a huge gap between the master
and develop
branch. Are you going to update master
anytime soon? If not, I guess I should rather make a new PR based on develop
.
@PhilippvK Can you pls. check https://github.com/Minres/RISCV_ISA_CoreDSL/tree/tum-ei-eda-mnemonics-pr if I got all changes?
@eyck looks fine for me. In case some mnemonics are missing, we can just add them in a follow-up PR. The CoreDSL passes the M2-ISA-R parser.
I realized that tum-ei-eda-mnemonics-pr
needs to be rebased on your master
to eliminate the conflicts...
Changes
assembly:
(Diff: https://github.com/Minres/RISCV_ISA_CoreDSL/commit/793b18a0a283fde033d14cc2f8804e1594f8f6dd){fname(rd)}
instead off {rd}
for float registers in assembly args (Diff: https://github.com/Minres/RISCV_ISA_CoreDSL/commit/c16a4cc32d821de6797939f14493f7ae177bdd7b)