These changes have been made while integrating the CoreDSL 2 generated RISC-V models in ETISS. Currently a RV32GC + Zicsr + Zifencei core passes all relevant tests of the RISC-V instruction test suite, except the instructions LR and SC; the ETISS model provides own implementations for these here. If interested, I would include them here.
Changes include but not limited to:
Many typing fixes
Formatting fixes
Memory access width fixes, mostly making sure that instructions will work for any XLEN
Changes to inheritance hierarchy to reflect the RISC-V reference manual
Set defaults for XLEN, FLEN, MUL_LEN in the ISA extensions
These changes have been made while integrating the CoreDSL 2 generated RISC-V models in ETISS. Currently a
RV32GC + Zicsr + Zifenceicore passes all relevant tests of the RISC-V instruction test suite, except the instructionsLRandSC; the ETISS model provides own implementations for these here. If interested, I would include them here.Changes include but not limited to:
XLENXLEN,FLEN,MUL_LENin the ISA extensions