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Minres / RISCV_ISA_CoreDSL

CoreDSL descriptions of the RISC-V ISA
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Address space accesses in load/store instructions are too narrow #4

Open jopperm opened 2 years ago

jopperm commented 2 years ago

Problem

We currently define the main memory address space as: https://github.com/Minres/RISCV_ISA_CoreDSL/blob/28abf7c055fd58ea33853a083c9a098135182467/RISCVBase.core_desc#L48

Then, a single index expression like in here: https://github.com/Minres/RISCV_ISA_CoreDSL/blob/28abf7c055fd58ea33853a083c9a098135182467/RV32I.core_desc#L129-L137 ... would only yield a char result (as declared), which is then wrongly sign-extended to 32-bits.

Possible solutions

  1. Make multiple loads and concatenation explicit. 
    X[rd] = MEM[base + 3] :: MEM[base + 2] :: MEM[base + 1] :: MEM[base + 0];
  2. Introduce a ranged index operator for CoreDSL (currently, this is only supported for bit ranges, and with constant indices!) 
    X[rd] = MEM[base+3:base];
  3. Make loads as wide as the assignment target, and stores as wide as the value to be written. This would be the first context-sensitive type rule in the language, and hence doesn't fit well into the overall semantics.
wysiwyng commented 2 years ago

in the case of M2-ISA-R, 3) is (and always was) done implicitly.