ar_ready incorrect timing diagram

[mslijepc]

In some cases, it appears incorrect timing diagram of ar_ready signal (half-cycle asserted signal).

[eyck]

This is valid according to the AXI spec as it is sampled on the rising edge of the clock. And the AXI spec states in section 'A3.2.1 Handshake process':

When VALID is asserted, it must remain asserted until the handshake occurs, at a rising clock edge when VALID and READY are both asserted.

I agree this is not nice but correct

[mslijepc]

How many transactions then in this case should be (i.e. how many valid addresses)?

[eyck]

The picture shows 5 transactions, 1 to the left of the cursor and 4 to the right. Whenever the condition ar_valid==1 && ar_ready==1 is tru right before the clock rises.