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Minres / SystemC-Components

A SystemC productivity library: https://minres.github.io/SystemC-Components/
https://www.minres.com/#opensource
Apache License 2.0
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Q: Un-aligned write #45

Open mslijepc opened 1 year ago

mslijepc commented 1 year ago

Hi Eyck, not sure if there is a bug in this line:

https://github.com/Minres/SystemC-Components/blob/7d8a0173b219d684c80ba268086b31027d4a7402/src/bus_interfaces/axi/pin/axi4_initiator.h#L174C13-L174C13

In case we have e.g. 32B wide bus, we want to have single 4B write, with an offset 30, strb will be all zeros. How this write should be handled?

eyck commented 1 year ago

I'll have a look...

mslijepc commented 1 year ago

and also, data will be all zeros. Not sure, by the spec, if this should be done as burst?

eyck commented 10 months ago

Hmm, I connot reproduce the issue although I tried hard ( found an issue with the second beat but not the first one) . This is what I get: grafik Did you attach an axi4_extension to the incoming transaction?

mslijepc commented 10 months ago

Yes, axi4_extension was attached. How do you reproduce error, can you manually set address and len?

eyck commented 10 months ago

Address and length are taken from the tlm_generic_payload so this way you can control it