Open mslijepc opened 10 months ago
Your proposed fix will not work. ready will be set and cleared by the rising edge of the initiator. The line you prose is being executed in the delta-cycle right after rising edge of the clock- becaus of this wait. But this is the deltacycle where the ready is cleared by the initiator (or maybe not). To me the the waveform looks like a back-to-back response of the target. Can you try to set the ready to 0 after the first response?
No, it's not back to back. This is the full waveform
For every response, we wait for have 2 cycles ready
and last
You are right.. Would then maybe this be correct?
else {
wait(clk_i.posedge_event());
}
We get the
r_last
andr_valid
for 2 cyclesI guess that it can be fixed, instead of
https://github.com/Minres/SystemC-Components/blob/ed4a529680204b25797e35ab7c9875b1d3ada50d/src/bus_interfaces/axi/pin/ace_target.h#L420
putting it in
else
Because in any case we wait for one cycle afterwards
https://github.com/Minres/SystemC-Components/blob/ed4a529680204b25797e35ab7c9875b1d3ada50d/src/bus_interfaces/axi/pin/ace_target.h#L428