MockbaTheBorg / MockbaModular

Mockba's plugin for VCV Rack
MIT License
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Feature Request for AndOr #8

Closed Stubs42 closed 4 years ago

Stubs42 commented 4 years ago

Hi, Like your modules very much. Often use a dualAnd and dualOr in combination. To reduce the number or modules, space usage and trigger timing issues. I would like to see a AndOr module. Just like a dual And but with an Or in the lower half of the module with the output of the upper And normaled to the first input of the lower Or if not patched. Use case is to run two trigger sequences through it. The first is patched to the lower Or input and the second to a And input. The second And input it patched to a rondom trigger source. So the first sequence will always trigger on AndOr output but the second will only trigger if both, the second sequence and the random trigger hit. Should be a no brainer and would help me a lot. Regards Dieter

MockbaTheBorg commented 4 years ago

Sure it can be done.

But before we go there: What you described is a "priority selector", where the signal port H (connected to the OR) always goes, has higher priority, and the signal on port L (connected to the AND) has lower priority, so it only goes when its priority is raised by the random trigger (also connected to the AND).

Unfortunately I have just released an update, so it would take some time until I release the next with a priority selector on it.

In the meantime, would "Selectah" help you?

Supposing all signals are triggers (0-10V), if you connect the higher priority trigger to Port A and the lower priority trigger to Port D, then your random trigger to the Mod input, the random trigger should select between ports A and D as if they were H and L. This might solve the problem for you with a single module.

Only problem is: it is not a priority selector, it is just a simple selector, so if the random trigger is high at a moment, Port A shall not pass. But depending on how exactly you are building the two original sequences, it might work exactly the same.

Please let me know.

Cheers, The Borg.

MockbaTheBorg commented 4 years ago

image

This is an example. First sequence is H, second sequence is L and third sequence simulates the random trigger.

Stubs42 commented 4 years ago

Hi, Maybe I'm wrong but I think the selectah solution will not work. As I understand, the select mod selects the input to send to the output. This would result in mod (NoteSeq[3]) being high, the input d is used, thus delivering no output if input d (NoteSeq[2]) is low even if input a (NoteSeq[1]) is high. The dualAnd/Or solution will always deliver an output if NoteSeq[1] is high no natter what the outputs of NoteSeq[2/3] are. If I did not understand selectah correctly, please let me know. Regards Dieter

MockbaTheBorg commented 4 years ago

Yes, you are correct. As I said, it could be a solution for the time being until I do another release. It only matches the and-or if the sequences are created to do so. If the sequences are random then it will not match. But again, maybe it would be similar enough. I personally use it all the time, maybe that's why I never thought of the and-or. But I will make one for the next release.

Thanks, Mockba

On Wed, Feb 5, 2020, 5:39 AM Stubs42 notifications@github.com wrote:

Hi, Maybe I'm wrong but I think the selectah solution will not work. As I understand, the select mod selects the input to send to the output. This would result in mod (NoteSeq[3]) being high, the input d is used, thus delivering no output if input d (NoteSeq[2]) is low even if input a (NoteSeq[1]) is high. The dualAnd/Or solution will always deliver an output if NoteSeq[1] is high no natter what the outputs of NoteSeq[2/3] are. If I did not understand selectah correctly, please let me know. Regards Dieter

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Stubs42 commented 4 years ago

Ok, Thx, was afraid I got it wrong. Looking forward to your next release :-) Anyway, I like your modules very much. Tiny and CPU friendly, Well done !

MockbaTheBorg commented 4 years ago

Hi @Stubs42 ,

I have implemented "PSelectah", a Priority Selector module which implements the AND->OR logic. It has two inputs: One called "low", which never goes out, unless its priority is raised by the "raise" input. These are the two ports of the AND. The "high" port always goes out. This if the OR port. Look for it on the next release, which should be out soon.

Cheers, Marcelo.