Open xinghot2007 opened 1 year ago
MrChromebox
commented
1 year ago the rcomp values are based on trace lengths on the board, they do no change based on memory type/amount installed.
to troubleshoot this, I would recommend a debug build of coreboot and a Suzy-Q cable so you can see why ram init is failing / see how the firmware is recognizing the installed memory and strap config
xinghot2007
commented
1 year ago Thank you for your advice!
I made a Suzy-Q cable and ccd CMD "version" show:
version Chip: g cr50 B2-C Board: 0 RO_A: 0.0.10/29d77172 RO_B: 0.0.11/4d655eab RW_A: 0.6.120/cr50_v3.94_pp.43-adfaeb3b2e RW_B: Error BID A: 46464646:00000000:00000010 Yes BID B: 46464646:00000000:00000010 Yes Build: 0.6.120/cr50_v3.94_pp.43-adfaeb3b2e tpm2:v1.9308_26_0.71-8b56d7c 2022-06-06 21:06:11 @chromeos-ci-firmware-us-east1-d-x32-0-n9s3
Is means the RW_B have some ERRORS?
When use make crossgcc,which suffix to use? the -i386 or the -x64.
when use make menuconfig,I can`t decision which options to enable.Especially the EC,my board is NPCX796.
when use make,the console show:
Success!
CC romstage/mainboard/google/hatch/static.o
CC romstage/acpi/acpi_pm.o
CC romstage/arch/x86/assembly_entry.o
CC romstage/arch/x86/boot.o
CC romstage/arch/x86/breakpoint.o
CP romstage/arch/x86/car.ld
CC romstage/arch/x86/cf9_reset.o
CC romstage/arch/x86/cpu_common.o
CC romstage/arch/x86/exception.o
CC romstage/arch/x86/gdt_init.o
CC romstage/arch/x86/idt.o
CC romstage/arch/x86/memcpy.o
CP romstage/arch/x86/memlayout.ld
CC romstage/arch/x86/memmove.o
CC romstage/arch/x86/memset.o
CC romstage/arch/x86/mmap_boot.o
CC romstage/arch/x86/null_breakpoint.o
CC romstage/arch/x86/post.o
CC romstage/arch/x86/postcar_loader.o
CC romstage/arch/x86/romstage.o
CC romstage/arch/x86/timestamp.o
CC romstage/commonlib/bsd/cbfs_mcache.o
CC romstage/commonlib/bsd/cbfs_private.o
CC romstage/commonlib/bsd/elog.o
CC romstage/commonlib/bsd/lz4_wrapper.o
CC romstage/commonlib/iobuf.o
CC romstage/commonlib/mem_pool.o
CC romstage/commonlib/rational.o
CC romstage/commonlib/region.o
CC romstage/console/console.o
CC romstage/console/die.o
CC romstage/console/init.o
CC romstage/console/post.o
CC romstage/console/printk.o
CC romstage/console/vsprintf.o
CC romstage/console/vtxprintf.o
CC romstage/cpu/intel/car/romstage.o
CC romstage/cpu/intel/microcode/microcode.o
CC romstage/cpu/x86/lapic/boot_cpu.o
CC romstage/cpu/x86/lapic/lapic.o
CC romstage/cpu/x86/mtrr/debug.o
CC romstage/cpu/x86/mtrr/earlymtrr.o
CC romstage/cpu/x86/name/name.o
CC romstage/cpu/x86/pae/pgtbl.o
CC romstage/cpu/x86/smm/tseg_region.o
CC romstage/cpu/x86/tsc/delay_tsc.o
CC romstage/device/device_const.o
CC romstage/device/dram/ddr2.o
CC romstage/device/dram/ddr3.o
CC romstage/device/dram/ddr4.o
CC romstage/device/dram/ddr5.o
CC romstage/device/dram/ddr_common.o
CC romstage/device/dram/lpddr4.o
CC romstage/device/i2c.o
CC romstage/device/mmio.o
CC romstage/device/pci_early.o
CC romstage/device/pci_ops.o
CC romstage/drivers/i2c/designware/dw_i2c.o
CC romstage/drivers/intel/fsp2_0/cbmem.o
CC romstage/drivers/intel/fsp2_0/debug.o
CC romstage/drivers/intel/fsp2_0/hand_off_block.o
CC romstage/drivers/intel/fsp2_0/header_display.o
CC romstage/drivers/intel/fsp2_0/hob_display.o
CC romstage/drivers/intel/fsp2_0/hob_verify.o
CC romstage/drivers/intel/fsp2_0/memory_init.o
CC romstage/drivers/intel/fsp2_0/upd_display.o
CC romstage/drivers/intel/fsp2_0/util.o
CC romstage/drivers/mrc_cache/mrc_cache.o
CC romstage/drivers/pc80/pc/i8254.o
CC romstage/drivers/pc80/rtc/mc146818rtc.o
CC romstage/drivers/pc80/rtc/mc146818rtc_boot.o
CC romstage/drivers/spi/bitbang.o
CC romstage/drivers/spi/boot_device_rw_nommap.o
CC romstage/drivers/spi/flashconsole.o
CC romstage/drivers/spi/spi-generic.o
CC romstage/drivers/spi/spi_flash.o
CC romstage/drivers/spi/tpm/tis.o
CC romstage/drivers/spi/tpm/tpm.o
CC romstage/drivers/tpm/cr50.o
CC romstage/drivers/uart/uart8250mem.o
CC romstage/drivers/uart/util.o
CC romstage/drivers/wifi/generic/generic.o
CC romstage/ec/google/chromeec/crosec_proto.o
CC romstage/ec/google/chromeec/ec.o
CC romstage/ec/google/chromeec/ec_boardid.o
CC romstage/ec/google/chromeec/ec_lpc.o
CC romstage/ec/google/chromeec/ec_skuid.o
CC romstage/ec/google/chromeec/ec_smbios.o
CC romstage/ec/google/chromeec/vstore.o
CC romstage/lib/boot_device.o
CC romstage/lib/bootmode.o
CC romstage/lib/cbfs.o
CC romstage/lib/cbmem_common.o
CC romstage/lib/cbmem_console.o
CC romstage/lib/compute_ip_checksum.o
CC romstage/lib/crc_byte.o
CC romstage/lib/delay.o
CC romstage/lib/dimm_info_util.o
CC romstage/lib/ext_stage_cache.o
CC romstage/lib/fmap.o
CC romstage/lib/gcc.o
CC romstage/lib/gpio.o
CC romstage/lib/halt.o
CC romstage/lib/hexdump.o
CC romstage/lib/imd.o
CC romstage/lib/imd_cbmem.o
CC romstage/lib/libgcc.o
CC romstage/lib/list.o
CC romstage/lib/lzma.o
CC romstage/lib/lzmadecode.o
CC romstage/lib/memchr.o
CC romstage/lib/memcmp.o
CC romstage/lib/memrange.o
CC romstage/lib/prog_loaders.o
CC romstage/lib/prog_ops.o
CP romstage/lib/program.ld
CC romstage/lib/ramtest.o
CC romstage/lib/region_file.o
CC romstage/lib/reset.o
CC romstage/lib/rmodule.o
CC romstage/lib/romstage_handoff.o
CC romstage/lib/rtc.o
CC romstage/lib/selfboot.o
CC romstage/lib/spd_bin.o
CC romstage/lib/stack.o
CC romstage/lib/string.o
CC romstage/lib/timestamp.o
CC romstage/lib/version.o
CC romstage/lib/xxhash.o
CC romstage/mainboard/google/hatch/romstage.o
CC romstage/mainboard/google/hatch/variants/baseboard/gpio.o
CC romstage/mainboard/google/hatch/variants/baseboard/memory.o
CC romstage/security/memory/memory.o
CC romstage/security/tpm/tspi/tspi.o
CC romstage/security/tpm/tss/tcg-2.0/tss.o
CC romstage/security/tpm/tss/tcg-2.0/tss_marshaling.o
CC romstage/security/tpm/tss/vendor/cr50/cr50.o
CC romstage/soc/intel/cannonlake/cnl_memcfg_init.o
CC romstage/soc/intel/cannonlake/gpio.o
CC romstage/soc/intel/cannonlake/gspi.o
CC romstage/soc/intel/cannonlake/i2c.o
CC romstage/soc/intel/cannonlake/lpc.o
CC romstage/soc/intel/cannonlake/pmutil.o
CC romstage/soc/intel/cannonlake/reset.o
CC romstage/soc/intel/cannonlake/romstage/fsp_params.o
CC romstage/soc/intel/cannonlake/romstage/romstage.o
CC romstage/soc/intel/cannonlake/romstage/systemagent.o
CC romstage/soc/intel/cannonlake/spi.o
CC romstage/soc/intel/cannonlake/uart.o
CC romstage/soc/intel/common/block/chip/chip.o
CC romstage/soc/intel/common/block/cpu/cpulib.o
CC romstage/soc/intel/common/block/cse/cse.o
CC romstage/soc/intel/common/block/fast_spi/fast_spi.o
CC romstage/soc/intel/common/block/fast_spi/fast_spi_flash.o
CC romstage/soc/intel/common/block/gpio/gpio.o
CC romstage/soc/intel/common/block/gpmr/gpmr.o
CC romstage/soc/intel/common/block/gspi/gspi.o
CC romstage/soc/intel/common/block/i2c/i2c.o
CC romstage/soc/intel/common/block/itss/itss.o
CC romstage/soc/intel/common/block/lpc/lpc_lib.o
CC romstage/soc/intel/common/block/lpss/lpss.o
CC romstage/soc/intel/common/block/p2sb/p2sb.o
CC romstage/soc/intel/common/block/p2sb/p2sblib.o
CC romstage/soc/intel/common/block/pcie/pcie_helpers.o
CC romstage/soc/intel/common/block/pcr/pcr.o
CC romstage/soc/intel/common/block/pmc/pmclib.o
CC romstage/soc/intel/common/block/rtc/rtc.o
CC romstage/soc/intel/common/block/smbus/smbus_early.o
CC romstage/soc/intel/common/block/smbus/smbuslib.o
CC romstage/soc/intel/common/block/smbus/tco.o
CC romstage/soc/intel/common/block/smm/smm.o
CC romstage/soc/intel/common/block/spi/spi.o
CC romstage/soc/intel/common/block/systemagent/memmap.o
CC romstage/soc/intel/common/block/systemagent/systemagent_early.o
CC romstage/soc/intel/common/block/thermal/thermal_common.o
CC romstage/soc/intel/common/block/thermal/thermal_pci.o
CC romstage/soc/intel/common/block/timer/timer.o
CC romstage/soc/intel/common/block/uart/uart.o
CC romstage/soc/intel/common/fsp_reset.o
CC romstage/soc/intel/common/reset.o
CC romstage/soc/intel/common/smbios.o
CC romstage/soc/intel/common/tpm_tis.o
CC romstage/southbridge/intel/common/smbus.o
LINK cbfs/fallback/romstage.debug
OBJCOPY cbfs/fallback/romstage.elf
CREATE build/mainboard/google/hatch/cbfs-file.RotliM.out (from /home/xinghot2007/coreboot/.config)
CC+STRIP src/lib/cbfs_master_header.c
CC+STRIP src/cpu/intel/fit/fit_table.c
LINK cbfs/fallback/bootblock.debug
/home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/arch/x86/exception.o: in function stub_putc': /home/xinghot2007/coreboot/src/arch/x86/exception.c:227: undefined reference togdb_tx_byte'
/home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:227:
/home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:227: undefined reference to gdb_tx_byte' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:227: undefined reference togdb_tx_byte'
/home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:227: undefined reference to gdb_tx_byte' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/arch/x86/exception.o: in functionstub_flush':
/home/xinghot2007/coreboot/src/arch/x86/exception.c:232: undefined reference to gdb_tx_flush' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/arch/x86/exception.o: in functionstub_getc':
/home/xinghot2007/coreboot/src/arch/x86/exception.c:237: undefined reference to gdb_rx_byte' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:237: undefined reference togdb_rx_byte'
/home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:237: undefined reference to gdb_rx_byte' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:237: undefined reference togdb_rx_byte'
/home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /home/xinghot2007/coreboot/src/arch/x86/exception.c:237: undefined reference to gdb_rx_byte' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/arch/x86/exception.o: in functionstub_putc':
/home/xinghot2007/coreboot/src/arch/x86/exception.c:227: undefined reference to gdb_tx_byte' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/arch/x86/exception.o: in functionstub_flush':
/home/xinghot2007/coreboot/src/arch/x86/exception.c:232: undefined reference to gdb_tx_flush' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/arch/x86/exception.o: in functionstub_putc':
/home/xinghot2007/coreboot/src/arch/x86/exception.c:227: undefined reference to gdb_tx_byte' /home/xinghot2007/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/arch/x86/exception.o: in functionstub_flush':
/home/xinghot2007/coreboot/src/arch/x86/exception.c:232: undefined reference to `gdb_tx_flush'
make: *** [src/arch/x86/Makefile.inc:103: build/cbfs/fallback/bootblock.debug] Error 1
I dont know whether it succeed or fail?
MrChromebox
commented
1 year ago I'd recommend cloning my repo, ensuring you have all required packages to build installed, then running make crossgcc-i386 then edit configs/cml/config.akemi.uefi to remove the line disabling serial output. save, then build by running ./build-ueif.sh akemi
xinghot2007
commented
1 year ago Under your advice,I cloned your repo.but I cannot find the line "disabling serial output" in configs/cml/config.akemi.uefi. So I add two lines to configs/cml/config.akemi.uefi like below:
CONFIG_CONSOLE_SERIAL=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
I don't hnow if that's right.
The debug msg: [NOTE ] coreboot-4.14-7726-g8a76e170c6-dirty-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC . [DEBUG] pm1_sts: 0900 pm1_en: 0000 pm1_cnt: 00001c00
[DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: a0054000 00000204 [DEBUG] GBLRST_CAUSE: 00000000 00000000 [DEBUG] HPR_CAUSE0: 00000000 [DEBUG] prev_sleep_state 5 [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes) [INFO ] CBFS: Found 'fspm.bin' @0x8bdc0 size 0x8e000 in mcache @0xfef21688 [DEBUG] FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes) [NOTE ] MRC: no data in 'RW_MRC_CACHE' [DEBUG] SPD INDEX = 6 [INFO ] CBFS: Found 'spd.bin' @0x60180 size 0xe00 in mcache @0xfef215c8 [INFO ] SPD: module type is DDR4 [INFO ] SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb [INFO ] SPD: device width 16 bits, bus width 64 bits [INFO ] SPD: module size is 4096 MB (per channel) [INFO ] memory slot: 0 configuration done. [INFO ] memory slot: 2 configuration done. [EMERG] FspMemoryInit returned with error 0x80000007!
MrChromebox
commented
1 year ago Under your advice,I cloned your repo.but I cannot find the line "disabling serial output" in configs/cml/config.akemi.uefi.
simply remove the line:
# CONFIG_CONSOLE_SERIAL is not set
so,
[DEBUG] SPD INDEX = 6
selects SPD_SOURCES += 8G_3200 # 0b110
this doesn't seem correct. That selection is for the module, not the total capacity. Selecting index 6 is correct for 4GB of DDR4-3200 RAM (I know this bc my 4GB AKEMI has index 6). What was the original SPD index/strapping of your board?
xinghot2007
commented
1 year ago My original SPD index is 6(use single channel).It is means bit not byte.
According to the schematic diagram,the motherboard DQMAP is below:
CHIP_NO DQSL_T DQSL_C DQSU_T DQSU_C
https://github.com/MrChromebox/coreboot/blob/2022.10.24/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h This cnl_mb_cfg struct shows dqs_map is only used by LPDDR.
Whether or not to define the dqs_map in this file: https://github.com/MrChromebox/coreboot/blob/2022.10.24/src/mainboard/google/hatch/variants/baseboard/memory.c
[NOTE ] MRC: no data in 'RW_MRC_CACHE' Whether or not it means the temp memory not init in FSP?
Thank you and best wishes!
xinghot2007
commented
1 year ago CHIP_NO DQSL_T DQSL_C DQSU_T DQSU_C
MrChromebox
commented
1 year ago My original SPD index is 6(use single channel).It is means bit not byte.
I understand how the GPIO straps work.
[NOTE ] MRC: no data in 'RW_MRC_CACHE' Whether or not it means the temp memory not init in FSP?
this means that RAM training was not successfully completed / that there is no cached RAM training data in the RW_MRC_CACHE region of the flash chip. This is expected after flashing the firmware until you successfully boot.
what is GPIO GPP_F2 (MEM_CH_SEL) set to? 0 (dual channel) or 1 (single channel)?
I'm fairly certain this isn't a DQ map issue.
xinghot2007
commented
1 year ago The GPIO GPP_F2 has connected to the ground with a 100k ohm resistor.(solder R679 to R682) I have already booked some micron’s ram chips for replace,because I found the 8GB version motherboard use these.I hope it works. Thank you and best wishes!
MrChromebox
commented
1 year ago was that something you added or already there? If the latter, could be why you weren't able to add more
I have upgraded my Chromebook (ideapad flex 5 13iml05) soldered 4GB RAM to 8GB RAM.(my device havs any larger RAM version)
I soldered the same original DDR4 modules(SAMSUNG K4A8G165WC BCWE) on the empty solder pad and changed MEM_CH_SEL to dual channel(solder R678 to R682).
chrome://system shows that channel 1 have nothing,the system cannot recognize the new 4GB RAM.So i flashed the UEFI firmware use your Firmware Utility Script.The chromebook cannot turn on.When i recover the MEM_CH_SEL to singer channel,the chromebook can boot.
My MEMORY CONFIG: MEM_STRAP_0 = 0 MEM_STRAP_1 = 1 MEM_STRAP_2 = 1 MEM_STRAP_3 = 0 https://github.com/MrChromebox/coreboot/blob/2022.07.08/src/mainboard/google/hatch/variants/akemi/Makefile.inc it's possible that firmware select the right SPD.
I doubt the DDR4 modules which i soldered were damaged, so i buy some new modules and soldered again.The problem is still.
I find this file: https://github.com/coreboot/coreboot/blob/master/src/mainboard/google/hatch/variants/baseboard/memory.c Rcomp resistors(R2 R3 R4) on my motherboard is 121 81 100,but i don`t understand the rest of code:
static const struct cnl_mb_cfg baseboard_memcfg = { / Baseboard uses 121, 81 and 100 rcomp resistors / .rcomp_resistor = {121, 81, 100},
};
How to measure the rcomp target values? How can the motherboard recognize my memory?
Thank you！