Samsung Chromebook Go (XE310XDA) - no touchpad, no camera

[kamahell87]

I followed the guide flashing the custom firmware on my chromebook and the whole process was very smooth.

When I booted up a Live Fedora, I noticed that the touchpad, the audio and the built-in camera didn't work. I tried different distros, even Endeavour and Manjaro, with the same result.

I ended up installing Debian 12 and this script to fix the audio and at the same time installing a custom kernel. Now the audio is working just fine, but the touchpad and the camera are still not getting detected by the system.

I double checked the hardware connection and everything well connected and not damaged.

I wonder if it something related to the firmware-util.sh (🤷) Speaking of the script, I noticed something interesting... I tried to run it again to see if there was an update to roll out, and there was one! So I installed it and rebooted the machine. When I get back to it, I wanted to satisfy myself by running your script again (expecting to see no updates available) but it showed the same update available. A bug, perhaps?

Thanks for your work!

[MrChromebox]

please provide cbmem output from a fresh boot, so I can verify that the firmware is detecting the touchpad. Audio and camera are completely OS/driver issues, not a firmware one

[kamahell87]

Here is the cbmem -c output:

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 bootblock starting (log level: 7)...
[DEBUG]  CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz
[DEBUG]  CPU: ID 906c0, Jasperlake A0, ucode: 24000024
[DEBUG]  CPU: AES supported, TXT NOT supported, VT supported
[DEBUG]  MCH: device id 4e22 (rev 00) is Jasperlake SKU4-1
[DEBUG]  PCH: device id 4d87 (rev 01) is Jasperlake Super
[DEBUG]  IGD: device id 4e55 (rev 01) is Jasperlake GT4
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0xc04000.
[DEBUG]  FMAP: base = 0xff000000 size = 0x1000000 #areas = 8
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: mcache @0xfef31a00 built for 19 files, used 0x3e0 of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x10b60 in mcache @0xfef31a2c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 1 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 romstage starting (log level: 7)...
[DEBUG]  pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00
[DEBUG]  gpe0_sts[0]: 00000010 gpe0_en[0]: 00000000
[DEBUG]  gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
[DEBUG]  gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG]  gpe0_sts[3]: 00080000 gpe0_en[3]: 00000000
[DEBUG]  TCO_STS:   0000 0001
[DEBUG]  GEN_PMCON: d0801038 00002200
[DEBUG]  GBLRST_CAUSE: 00000040 00000000
[DEBUG]  prev_sleep_state 5
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'fspm.bin' @0x68dc0 size 0x79000 in mcache @0xfef31c98
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[DEBUG]  SPD INDEX = 0
[INFO ]  CBFS: Found 'spd.bin' @0x368c0 size 0x200 in mcache @0xfef31bd8
[INFO ]  SPD: module type is LPDDR4X
[INFO ]  SPD: module part number is                     
[INFO ]  SPD: banks 8, ranks 1, rows 16, columns 10, density 16384 Mb
[INFO ]  SPD: device width 16 bits, bus width 32 bits
[INFO ]  SPD: module size is 4096 MB (per channel)
[INFO ]  meminit_channels: DRAM half-populated
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x76fff000 254 entries.
[DEBUG]  IMD: root @ 0x76ffec00 62 entries.
[DEBUG]  FMAP: area RO_VPD found @ c00000 (16384 bytes)
[WARN ]  init_vpd_rdev: No RW_VPD FMAP section.
[DEBUG]  External stage cache:
[DEBUG]  IMD: root @ 0x7b3ff000 254 entries.
[DEBUG]  IMD: root @ 0x7b3fec00 62 entries.
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG]  MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG]  cse_lite: Number of partitions = 3
[DEBUG]  cse_lite: Current partition = RW
[DEBUG]  cse_lite: Next partition = RW
[DEBUG]  cse_lite: Flags = 0x7
[DEBUG]  cse_lite: RO version = 13.50.11.1304 (Status=0x0, Start=0x1000, End=0xebfff)
[DEBUG]  cse_lite: RW version = 13.50.11.1304 (Status=0x0, Start=0x140000, End=0x2c2fff)
[DEBUG]  1 DIMMs found
[DEBUG]  SMM Memory Map
[DEBUG]  SMRAM       : 0x7b000000 0x800000
[DEBUG]   Subregion 0: 0x7b000000 0x200000
[DEBUG]   Subregion 1: 0x7b200000 0x200000
[DEBUG]   Subregion 2: 0x7b400000 0x400000
[DEBUG]  top_of_ram = 0x77000000
[DEBUG]  Normal boot
[INFO ]  CBFS: Found 'fallback/postcar' @0x118740 size 0x56d4 in mcache @0xfef31d0c
[DEBUG]  Loading module at 0x76c1f000 with entry 0x76c1f031. filesize: 0x5348 memsize: 0xb698
[DEBUG]  Processing 211 relocs. Offset value of 0x74c1f000
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 2 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 postcar starting (log level: 7)...
[DEBUG]  Normal boot
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'fallback/ramstage' @0x15d40 size 0x1f5e8 in mcache @0x76c2d10c
[DEBUG]  Loading module at 0x76bc6000 with entry 0x76bc6000. filesize: 0x42ad0 memsize: 0x57ed0
[DEBUG]  Processing 4633 relocs. Offset value of 0x72bc6000
[DEBUG]  BS: postcar times (exec / console): total (unknown) / 0 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 ramstage starting (log level: 7)...
[DEBUG]  Normal boot
[INFO ]  FW_CONFIG value from CBI is 0x60000040000
[INFO ]  fw_config match found: AUDIO_AMP=UNPROVISIONED
[INFO ]  GENERIC: 0.0 disabled by fw_config
[DEBUG]  microcode: sig=0x906c0 pf=0x1 revision=0x24000024
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0x10c80 size 0x5000 in mcache @0x76c2d0ac
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CBFS: Found 'fsps.bin' @0xe1e00 size 0x36906 in mcache @0x76c2d2d8
[DEBUG]  Detected 2 core, 2 thread CPU.
[DEBUG]  Setting up SMI for CPU
[DEBUG]  IED base = 0x7b400000
[DEBUG]  IED size = 0x00400000
[INFO ]  Will perform SMM setup.
[INFO ]  CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  CPU: APIC: 00 enabled
[DEBUG]  CPU: APIC: 01 enabled
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 16 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 1 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x2 in XAPIC mode.
[INFO ]  AP: slot 1 apic_id 2, MCU rev: 0x24000024
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x198 memsize: 0x198
[DEBUG]  Processing 9 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x76be45cd
[DEBUG]  Installing permanent SMM handler to 0x7b000000
[DEBUG]  HANDLER      [0x7b1fc000-0x7b1ff6e8]

[DEBUG]  CPU 0
[DEBUG]    ss0        [0x7b1fbc00-0x7b1fc000]
[DEBUG]    stub0      [0x7b1f4000-0x7b1f4198]

[DEBUG]  CPU 1
[DEBUG]    ss1        [0x7b1fb800-0x7b1fbc00]
[DEBUG]    stub1      [0x7b1f3c00-0x7b1f3d98]

[DEBUG]  stacks       [0x7b000000-0x7b001000]
[DEBUG]  Loading module at 0x7b1fc000 with entry 0x7b1fca26. filesize: 0x3638 memsize: 0x36e8
[DEBUG]  Processing 182 relocs. Offset value of 0x7b1fc000
[DEBUG]  Loading module at 0x7b1f4000 with entry 0x7b1f4000. filesize: 0x198 memsize: 0x198
[DEBUG]  Processing 9 relocs. Offset value of 0x7b1f4000
[DEBUG]  smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x200000
[DEBUG]  SMM Module: placing smm entry code at 7b1f3c00,  cpu # 0x1
[DEBUG]  SMM Module: stub loaded at 7b1f4000. Will call 0x7b1fca26
[DEBUG]  Clearing SMI status registers
[DEBUG]  SMI_STS: PM1 
[DEBUG]  PM1_STS: WAK PWRBTN 
[DEBUG]  TCO_STS: INTRD_DET 
[DEBUG]  GPE0 STD STS: 
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ec000, cpu = 0
[DEBUG]  In relocation handler: CPU 0
[DEBUG]  New SMBASE=0x7b1ec000 IEDBASE=0x7b400000
[DEBUG]  Writing SMRR. base = 0x7b000006, mask=0xff800c00
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ebc00, cpu = 1
[DEBUG]  In relocation handler: CPU 1
[DEBUG]  New SMBASE=0x7b1ebc00 IEDBASE=0x7b400000
[DEBUG]  Writing SMRR. base = 0x7b000006, mask=0xff800c00
[DEBUG]  Relocation complete.
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 906c0
[DEBUG]  CPU: family 06, model 9c, stepping 00
[DEBUG]  Clearing out pending MCEs
[INFO ]  Turbo is available but hidden
[INFO ]  Turbo is available and visible
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #1
[DEBUG]  CPU: vendor Intel device 906c0
[DEBUG]  CPU: family 06, model 9c, stepping 00
[DEBUG]  Clearing out pending MCEs
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CPU #1 initialized
[INFO ]  bsp_do_flight_plan done after 1 msecs.
[DEBUG]  CPU: frequency set to 2800 MHz
[DEBUG]  Enabling SMIs.
[DEBUG]  BS: BS_DEV_INIT_CHIPS entry times (exec / console): 41 / 0 ms
[INFO ]  Probing TPM: . done!
[INFO ]  TPM ready after 0 ms
[INFO ]  Connected to device vid:did:rid of 1ae0:0028:00
[INFO ]  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_A:0.5.215/cr50_v2.94_mp.294-221da5d8be
[INFO ]  Current CR50_BOARD_CFG = 0x00000000, setting to 0x00000001
[INFO ]  Initialized TPM device CR50 revision 0
[INFO ]  CBFS: Found 'vbt.bin' @0x68880 size 0x4b4 in mcache @0x76c2d268
[INFO ]  Found a VBT of 7680 bytes
[DEBUG]  WEAK: src/soc/intel/jasperlake/fsp_params.c/mainboard_silicon_init_params called
[DEBUG]  Detected 2 core, 2 thread CPU.
[DEBUG]  Detected 2 core, 2 thread CPU.
[INFO ]  FSPS returned 0
[DEBUG]  Display FSP Version Info HOB
[DEBUG]  Reference Code - CPU = 8.7.22.30
[DEBUG]  uCode Version = 24.0.0.24
[DEBUG]  TXT ACM version = ff.ff.ff.ffff
[DEBUG]  Reference Code - ME = 8.7.22.30
[DEBUG]  MEBx version = 0.0.0.0
[DEBUG]  ME Firmware Version = Lite SKU
[DEBUG]  Reference Code - PCH = 8.7.22.30
[DEBUG]  PCH-CRID Status = Disabled
[DEBUG]  PCH-CRID Original Value = ff.ff.ff.ffff
[DEBUG]  PCH-CRID New Value = ff.ff.ff.ffff
[DEBUG]  OPROM - RST - RAID = ff.ff.ff.ffff
[DEBUG]  PCH Hsio Version = 4.0.0.0
[DEBUG]  Reference Code - SA - System Agent = 8.7.22.30
[DEBUG]  Reference Code - MRC = 0.0.4.68
[DEBUG]  SA - PCIe Version = 8.7.22.30
[DEBUG]  SA-CRID Status = Disabled
[DEBUG]  SA-CRID Original Value = 0.0.0.0
[DEBUG]  SA-CRID New Value = 0.0.0.0
[DEBUG]  OPROM - VBIOS = ff.ff.ff.ffff
[DEBUG]  IO Manageability Engine FW Version = ff.ff.ff.ffff
[DEBUG]  PHY Build Version = ff.ff.ff.ffff
[DEBUG]  Thunderbolt(TM) FW Version = ff.ff.ff.ffff
[DEBUG]  System Agent Manageability Engine FW Version = ff.ff.ff.ffff
[DEBUG]  BS: BS_DEV_INIT_CHIPS run times (exec / console): 144 / 0 ms
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 0000 enabled
[DEBUG]  DOMAIN: 0000 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 00
[DEBUG]  PCI: 00:00.0 [8086/4e22] enabled
[DEBUG]  PCI: 00:02.0 [8086/4e55] enabled
[DEBUG]  PCI: 00:04.0 [8086/4e03] enabled
[DEBUG]  PCI: 00:08.0 [8086/4e11] enabled
[DEBUG]  PCI: 00:14.0 [8086/4ded] enabled
[DEBUG]  PCI: 00:14.2 [8086/4def] disabled
[DEBUG]  PCI: 00:14.3 [8086/4df0] enabled
[DEBUG]  PCI: 00:14.5 [8086/4df8] enabled
[DEBUG]  PCI: 00:15.0 [8086/4de8] enabled
[DEBUG]  PCI: 00:15.1 [8086/4de9] enabled
[DEBUG]  PCI: 00:15.2 [8086/4dea] enabled
[DEBUG]  PCI: 00:15.3 [8086/4deb] enabled
[DEBUG]  PCI: 00:16.0 [8086/4de0] enabled
[DEBUG]  PCI: 00:19.0 [8086/4dc5] enabled
[DEBUG]  PCI: 00:19.2 [8086/4dc7] enabled
[DEBUG]  PCI: 00:1a.0 [8086/4dc4] enabled
[DEBUG]  PCI: 00:1e.0 [8086/4da8] disabled
[DEBUG]  PCI: 00:1e.2 [8086/4daa] enabled
[DEBUG]  PCI: 00:1f.0 [8086/4d87] enabled
[INFO ]  PCI: Static device PCI: 00:1f.1 not found, disabling it.
[DEBUG]  RTC Init
[INFO ]  Set power on after power failure.
[DEBUG]  Disabling Deep S3
[DEBUG]  Disabling Deep S3
[DEBUG]  Disabling Deep S4
[DEBUG]  Disabling Deep S4
[DEBUG]  Disabling Deep S5
[DEBUG]  Disabling Deep S5
[DEBUG]  PCI: 00:1f.2 [0000/0000] hidden
[DEBUG]  PCI: 00:1f.3 [8086/4dc8] enabled
[DEBUG]  PCI: 00:1f.5 [8086/4da4] enabled
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:12.6
[WARN ]  PCI: 00:05.0
[WARN ]  PCI: 00:09.0
[WARN ]  PCI: 00:14.1
[WARN ]  PCI: 00:16.1
[WARN ]  PCI: 00:16.4
[WARN ]  PCI: 00:16.5
[WARN ]  PCI: 00:17.0
[WARN ]  PCI: 00:19.1
[WARN ]  PCI: 00:1e.1
[WARN ]  PCI: 00:1e.3
[WARN ]  PCI: 00:1f.1
[WARN ]  PCI: 00:1f.4
[WARN ]  PCI: 00:1f.7
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:02.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:02.0 finished in 0 msecs
[DEBUG]  PCI: 00:04.0 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  bus: PCI: 00:04.0[0]->scan_bus: bus PCI: 00:04.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.0 scanning...
[DEBUG]  USB0 port 0 enabled
[DEBUG]  USB0 port 0 scanning...
[DEBUG]  USB2 port 0 enabled
[DEBUG]  USB2 port 1 enabled
[DEBUG]  USB2 port 2 enabled
[DEBUG]  USB2 port 3 enabled
[DEBUG]  USB2 port 4 disabled
[DEBUG]  USB2 port 5 enabled
[DEBUG]  USB2 port 6 disabled
[DEBUG]  USB2 port 7 enabled
[DEBUG]  USB3 port 0 enabled
[DEBUG]  USB3 port 1 enabled
[DEBUG]  USB3 port 2 enabled
[DEBUG]  USB3 port 3 enabled
[DEBUG]  USB2 port 0 scanning...
[DEBUG]  scan_bus: bus USB2 port 0 finished in 0 msecs
[DEBUG]  USB2 port 1 scanning...
[DEBUG]  scan_bus: bus USB2 port 1 finished in 0 msecs
[DEBUG]  USB2 port 2 scanning...
[DEBUG]  scan_bus: bus USB2 port 2 finished in 0 msecs
[DEBUG]  USB2 port 3 scanning...
[DEBUG]  scan_bus: bus USB2 port 3 finished in 0 msecs
[DEBUG]  USB2 port 5 scanning...
[DEBUG]  scan_bus: bus USB2 port 5 finished in 0 msecs
[DEBUG]  USB2 port 7 scanning...
[DEBUG]  scan_bus: bus USB2 port 7 finished in 0 msecs
[DEBUG]  USB3 port 0 scanning...
[DEBUG]  scan_bus: bus USB3 port 0 finished in 0 msecs
[DEBUG]  USB3 port 1 scanning...
[DEBUG]  scan_bus: bus USB3 port 1 finished in 0 msecs
[DEBUG]  USB3 port 2 scanning...
[DEBUG]  scan_bus: bus USB3 port 2 finished in 0 msecs
[DEBUG]  USB3 port 3 scanning...
[DEBUG]  scan_bus: bus USB3 port 3 finished in 0 msecs
[DEBUG]  scan_bus: bus USB0 port 0 finished in 0 msecs
[DEBUG]  scan_bus: bus PCI: 00:14.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.3 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:14.3 finished in 0 msecs
[DEBUG]  PCI: 00:15.0 scanning...
[DEBUG]  I2C: 00:15 enabled
[DEBUG]  I2C: 00:40 enabled
[DEBUG]  scan_bus: bus PCI: 00:15.0 finished in 0 msecs
[DEBUG]  PCI: 00:15.1 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.1 finished in 0 msecs
[DEBUG]  PCI: 00:15.2 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.2 finished in 0 msecs
[DEBUG]  PCI: 00:15.3 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.3 finished in 0 msecs
[DEBUG]  PCI: 00:19.0 scanning...
[DEBUG]  I2C: 00:1a enabled
[DEBUG]  scan_bus: bus PCI: 00:19.0 finished in 0 msecs
[DEBUG]  PCI: 00:1e.2 scanning...
[DEBUG]  SPI: 00 enabled
[DEBUG]  bus: PCI: 00:1e.2[0]->scan_bus: bus PCI: 00:1e.2 finished in 0 msecs
[DEBUG]  PCI: 00:1f.0 scanning...
[DEBUG]  PNP: 0c09.0 enabled
[DEBUG]  PNP: 0c09.0 scanning...
[DEBUG]  scan_bus: bus PNP: 0c09.0 finished in 0 msecs
[DEBUG]  scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
[DEBUG]  PCI: 00:1f.3 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  GENERIC: 0.0 disabled
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
[DEBUG]  scan_bus: bus DOMAIN: 0000 finished in 1 msecs
[DEBUG]  scan_bus: bus Root Device finished in 1 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms
[INFO ]  MRC: Could not find region 'UNIFIED_MRC_CACHE'
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[INFO ]  MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
[DEBUG]  found VGA at PCI: 00:02.0
[DEBUG]  Setting up VGA for PCI: 00:02.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[DEBUG]  SA MMIO resource: PCIEXBAR ->  base = 0xc0000000, size = 0x10000000
[DEBUG]  SA MMIO resource: MCHBAR   ->  base = 0xfea80000, size = 0x00008000
[DEBUG]  SA MMIO resource: DMIBAR   ->  base = 0xfeda0000, size = 0x00001000
[DEBUG]  SA MMIO resource: EPBAR    ->  base = 0xfeda1000, size = 0x00001000
[DEBUG]  SA MMIO resource: REGBAR   ->  base = 0xfb000000, size = 0x00001000
[DEBUG]  SA MMIO resource: EDRAMBAR ->  base = 0xfed80000, size = 0x00004000
[DEBUG]  SA MMIO resource: GFXVTBAR ->  base = 0xfed90000, size = 0x00001000
[DEBUG]  SA MMIO resource: IPUVTBAR ->  base = 0xfed92000, size = 0x00001000
[DEBUG]  SA MMIO resource: VTVC0BAR ->  base = 0xfed91000, size = 0x00001000
[INFO ]  Available memory above 4GB: 2052M
[INFO ]  Done reading resources.
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 1 (relative placement) ===
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 84 base 00000800 limit 000008ff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 88 base 00000200 limit 0000020f io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 8c base 00000900 limit 000009ff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 90 base 00000080 limit 0000008f io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 1000, Size: 800, Tag: 100
[INFO ]   * Base: 1900, Size: e700, Tag: 100
[DEBUG]    PCI: 00:02.0 20 *  [0x1000 - 0x103f] limit: 103f io
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 0000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff
[DEBUG]  DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 01 base fea80000 limit fea87fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 08 base fed91000 limit fed91fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0a base 000c0000 limit 76ffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0b base 77000000 limit 7fbfffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0c base 100000000 limit 1803fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0d base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0e base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:19.2 10 base fe032000 limit fe032fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 98 base fe0b0000 limit fe0bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.2 10 base fe000000 limit fe00ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.5 00 base ff000000 limit ffffffff mem (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 7fc00000, Size: 40400000, Tag: 200
[INFO ]   * Base: d0000000, Size: 10000000, Tag: 200
[INFO ]   * Base: 180400000, Size: 7e7fc00000, Tag: 200
[DEBUG]    PCI: 00:02.0 18 *  [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
[DEBUG]    PCI: 00:02.0 10 *  [0x90000000 - 0x90ffffff] limit: 90ffffff mem
[DEBUG]    PCI: 00:1f.3 20 *  [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
[DEBUG]    PCI: 00:04.0 10 *  [0x7fd00000 - 0x7fd0ffff] limit: 7fd0ffff mem
[DEBUG]    PCI: 00:14.0 10 *  [0x7fd10000 - 0x7fd1ffff] limit: 7fd1ffff mem
[DEBUG]    PCI: 00:14.3 10 *  [0x7fd20000 - 0x7fd23fff] limit: 7fd23fff mem
[DEBUG]    PCI: 00:1f.3 10 *  [0x7fd24000 - 0x7fd27fff] limit: 7fd27fff mem
[DEBUG]    PCI: 00:08.0 10 *  [0x7fd28000 - 0x7fd28fff] limit: 7fd28fff mem
[DEBUG]    PCI: 00:14.5 10 *  [0x7fd29000 - 0x7fd29fff] limit: 7fd29fff mem
[DEBUG]    PCI: 00:15.0 10 *  [0x7fd2a000 - 0x7fd2afff] limit: 7fd2afff mem
[DEBUG]    PCI: 00:15.1 10 *  [0x7fd2b000 - 0x7fd2bfff] limit: 7fd2bfff mem
[DEBUG]    PCI: 00:15.2 10 *  [0x7fd2c000 - 0x7fd2cfff] limit: 7fd2cfff mem
[DEBUG]    PCI: 00:15.3 10 *  [0x7fd2d000 - 0x7fd2dfff] limit: 7fd2dfff mem
[DEBUG]    PCI: 00:16.0 10 *  [0x7fd2e000 - 0x7fd2efff] limit: 7fd2efff mem
[DEBUG]    PCI: 00:19.0 10 *  [0x7fd2f000 - 0x7fd2ffff] limit: 7fd2ffff mem
[DEBUG]    PCI: 00:19.2 18 *  [0x7fd30000 - 0x7fd30fff] limit: 7fd30fff mem
[DEBUG]    PCI: 00:1a.0 10 *  [0x7fd31000 - 0x7fd31fff] limit: 7fd31fff mem
[DEBUG]    PCI: 00:1e.2 10 *  [0x7fd32000 - 0x7fd32fff] limit: 7fd32fff mem
[DEBUG]    PCI: 00:1f.5 10 *  [0x7fd33000 - 0x7fd33fff] limit: 7fd33fff mem
[DEBUG]  DOMAIN: 0000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff done
[DEBUG]  DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[DEBUG]  PCI: 00:02.0 10 <- [0x0000000090000000 - 0x0000000090ffffff] size 0x01000000 gran 0x18 mem64
[DEBUG]  PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG]  PCI: 00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
[DEBUG]  PCI: 00:04.0 10 <- [0x000000007fd00000 - 0x000000007fd0ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:08.0 10 <- [0x000000007fd28000 - 0x000000007fd28fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:14.0 10 <- [0x000000007fd10000 - 0x000000007fd1ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:14.3 10 <- [0x000000007fd20000 - 0x000000007fd23fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:14.5 10 <- [0x000000007fd29000 - 0x000000007fd29fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.0 10 <- [0x000000007fd2a000 - 0x000000007fd2afff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.1 10 <- [0x000000007fd2b000 - 0x000000007fd2bfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.2 10 <- [0x000000007fd2c000 - 0x000000007fd2cfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.3 10 <- [0x000000007fd2d000 - 0x000000007fd2dfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:16.0 10 <- [0x000000007fd2e000 - 0x000000007fd2efff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:19.0 10 <- [0x000000007fd2f000 - 0x000000007fd2ffff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:19.2 18 <- [0x000000007fd30000 - 0x000000007fd30fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1a.0 10 <- [0x000000007fd31000 - 0x000000007fd31fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1e.2 10 <- [0x000000007fd32000 - 0x000000007fd32fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1f.3 10 <- [0x000000007fd24000 - 0x000000007fd27fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:1f.3 20 <- [0x000000007fc00000 - 0x000000007fcfffff] size 0x00100000 gran 0x14 mem64
[DEBUG]  PCI: 00:1f.5 10 <- [0x000000007fd33000 - 0x000000007fd33fff] size 0x00001000 gran 0x0c mem
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 3 / 0 ms
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00.0 subsystem <- 8086/4e22
[DEBUG]  PCI: 00:00.0 cmd <- 06
[DEBUG]  PCI: 00:02.0 subsystem <- 8086/4e55
[DEBUG]  PCI: 00:02.0 cmd <- 03
[DEBUG]  PCI: 00:04.0 subsystem <- 8086/4e03
[DEBUG]  PCI: 00:04.0 cmd <- 02
[DEBUG]  PCI: 00:08.0 subsystem <- 8086/4e11
[DEBUG]  PCI: 00:08.0 cmd <- 06
[DEBUG]  PCI: 00:14.0 subsystem <- 8086/4ded
[DEBUG]  PCI: 00:14.0 cmd <- 02
[DEBUG]  PCI: 00:14.3 subsystem <- 8086/4df0
[DEBUG]  PCI: 00:14.3 cmd <- 02
[DEBUG]  PCI: 00:14.5 subsystem <- 8086/4df8
[DEBUG]  PCI: 00:14.5 cmd <- 06
[DEBUG]  PCI: 00:15.0 subsystem <- 8086/4de8
[DEBUG]  PCI: 00:15.0 cmd <- 02
[DEBUG]  PCI: 00:15.1 subsystem <- 8086/4de9
[DEBUG]  PCI: 00:15.1 cmd <- 02
[DEBUG]  PCI: 00:15.2 subsystem <- 8086/4dea
[DEBUG]  PCI: 00:15.2 cmd <- 02
[DEBUG]  PCI: 00:15.3 subsystem <- 8086/4deb
[DEBUG]  PCI: 00:15.3 cmd <- 02
[DEBUG]  PCI: 00:16.0 subsystem <- 8086/4de0
[DEBUG]  PCI: 00:16.0 cmd <- 02
[DEBUG]  PCI: 00:19.0 subsystem <- 8086/4dc5
[DEBUG]  PCI: 00:19.0 cmd <- 02
[DEBUG]  PCI: 00:19.2 subsystem <- 8086/4dc7
[DEBUG]  PCI: 00:19.2 cmd <- 06
[DEBUG]  PCI: 00:1a.0 subsystem <- 8086/4dc4
[DEBUG]  PCI: 00:1a.0 cmd <- 06
[DEBUG]  PCI: 00:1e.2 subsystem <- 8086/4daa
[DEBUG]  PCI: 00:1e.2 cmd <- 06
[DEBUG]  PCI: 00:1f.0 subsystem <- 8086/4d87
[DEBUG]  PCI: 00:1f.0 cmd <- 407
[DEBUG]  PCI: 00:1f.3 subsystem <- 8086/4dc8
[DEBUG]  PCI: 00:1f.3 cmd <- 02
[DEBUG]  PCI: 00:1f.5 subsystem <- 8086/4da4
[DEBUG]  PCI: 00:1f.5 cmd <- 406
[INFO ]  done.
[INFO ]  Initializing devices...
[DEBUG]  Root Device init
[INFO ]  mainboard: EC init
[DEBUG]  Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG]  Chrome EC: UHEPI supported
[DEBUG]  Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
[DEBUG]  Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
[DEBUG]  Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001009105e
[DEBUG]  Chrome EC: Set WAKE mask to 0x0000000000000000
[DEBUG]  Root Device init finished in 1 msecs
[DEBUG]  PCI: 00:00.0 init
[INFO ]  CPU TDP = 6 Watts
[INFO ]  CPU PL1 = 6 Watts
[INFO ]  CPU PL2 = 20 Watts
[DEBUG]  PCI: 00:00.0 init finished in 1 msecs
[DEBUG]  PCI: 00:02.0 init
[INFO ]  GMA: Found VBT in CBFS
[INFO ]  GMA: Found valid VBT in CBFS
[INFO ]  framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32
[INFO ]                     x_res x y_res: 1366 x 768, size: 4227072 at 0x80000000
[DEBUG]  PCI: 00:02.0 init finished in 0 msecs
[DEBUG]  PCI: 00:08.0 init
[DEBUG]  PCI: 00:08.0 init finished in 0 msecs
[DEBUG]  PCI: 00:14.0 init
[DEBUG]  XHCI: Updated LFPS sampling OFF time to 9 ms
[DEBUG]  PCI: 00:14.0 init finished in 0 msecs
[DEBUG]  PCI: 00:15.0 init
[DEBUG]  I2C bus 0 version 0x3230302a
[INFO ]  DW I2C bus 0 at 0x7fd2a000 (400 KHz)
[DEBUG]  PCI: 00:15.0 init finished in 0 msecs
[DEBUG]  PCI: 00:15.1 init
[DEBUG]  I2C bus 1 version 0x3230302a
[INFO ]  DW I2C bus 1 at 0x7fd2b000 (400 KHz)
[DEBUG]  PCI: 00:15.1 init finished in 0 msecs
[DEBUG]  PCI: 00:15.2 init
[DEBUG]  I2C bus 2 version 0x3230302a
[INFO ]  DW I2C bus 2 at 0x7fd2c000 (400 KHz)
[DEBUG]  PCI: 00:15.2 init finished in 0 msecs
[DEBUG]  PCI: 00:15.3 init
[DEBUG]  I2C bus 3 version 0x3230302a
[INFO ]  DW I2C bus 3 at 0x7fd2d000 (400 KHz)
[DEBUG]  PCI: 00:15.3 init finished in 0 msecs
[DEBUG]  PCI: 00:16.0 init
[DEBUG]  PCI: 00:16.0 init finished in 0 msecs
[DEBUG]  PCI: 00:19.0 init
[DEBUG]  I2C bus 4 version 0x3230302a
[INFO ]  DW I2C bus 4 at 0x7fd2f000 (400 KHz)
[DEBUG]  PCI: 00:19.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1a.0 init
[DEBUG]  PCI: 00:1a.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1f.0 init
[DEBUG]  IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: ID = 0x00
[DEBUG]  IOAPIC: 120 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[DEBUG]  PCI: 00:1f.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1f.2 init
[DEBUG]  apm_control: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  PCI: 00:1f.2 init finished in 1 msecs
[DEBUG]  PCI: 00:1f.3 init
[DEBUG]  PCI: 00:1f.3 init finished in 0 msecs
[DEBUG]  PNP: 0c09.0 init
[DEBUG]  Google Chrome EC: Initializing
[DEBUG]  Google Chrome EC uptime: 3.110 seconds
[DEBUG]  Google Chrome AP resets since EC boot: 1
[DEBUG]  Google Chrome most recent AP reset causes:
[DEBUG]     0.395: 32775 shutdown: entering G3
[DEBUG]  Google Chrome EC reset flags at last EC boot: reset-pin | power-on | sysjump
[DEBUG]  Google Chrome EC: version:
[DEBUG]     ro: sasukette_v2.0.10540-df222fb19
[DEBUG]     rw: sasukette_v2.0.22514-05e2f7f803
[DEBUG]    running image: 2
[INFO ]  CBFS: Found 'ecrw.hash' @0x68800 size 0x20 in mcache @0x76c2d244
[DEBUG]  ChromeEC SW Sync: Expected hash: 01f3b2044c741b45d57c535f5c68daf0c59cb910ffd1d76a27516c706880a0ec
[DEBUG]  ChromeEC: Getting hash:
[DEBUG]  ChromeEC: No valid hash (status=0 size=0). Compute one...
[DEBUG]  ChromeEC: Starting EC hash:
[DEBUG]  ChromeEC SW Sync: current EC_RW hash: b14cca7d78a45093c344d2ae3d6e5738ae57d21a595b435dbf55586854339b51
[DEBUG]  ChromeEC SW Sync: updating EC_RW...
[INFO ]  CBFS: Found 'ecrw' @0x39f80 size 0x2e85c in mcache @0x76c2d224
[DEBUG]  Getting EC region info
[ERROR]  ChromeEC SW Sync: Failed to update EC_RW.
[ERROR]  ChromeEC: EC SW SYNC FAILED
[DEBUG]  PNP: 0c09.0 init finished in 643 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 649 / 0 ms
[DEBUG]  FMAP: area SMMSTORE found @ bc0000 (262144 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG]  smm store: 4 # blocks with size 0x10000
[INFO ]  SMMSTORE: Setting up SMI handler
[INFO ]  tlcl_send_startup: Startup return code is 0x0
[INFO ]  TPM: setup succeeded
[DEBUG]  BS: BS_DEV_INIT exit times (exec / console): 58 / 0 ms
[INFO ]  Finalize devices...
[DEBUG]  PCI: 00:02.0 final
[DEBUG]  PCI: 00:16.0 final
[DEBUG]  CSE RW Firmware Version: 0.0.0.0
[DEBUG]  PCI: 00:1f.2 final
[INFO ]  Devices finalized
[DEBUG]  ME: HFSTS1                      : 0x90000245
[DEBUG]  ME: HFSTS2                      : 0x82100136
[DEBUG]  ME: HFSTS3                      : 0x00000050
[DEBUG]  ME: HFSTS4                      : 0x00004000
[DEBUG]  ME: HFSTS5                      : 0x00000000
[DEBUG]  ME: HFSTS6                      : 0x40400006
[DEBUG]  ME: Manufacturing Mode          : NO
[DEBUG]  ME: SPI Protection Mode Enabled : YES
[DEBUG]  ME: FW Partition Table          : OK
[DEBUG]  ME: Bringup Loader Failure      : NO
[DEBUG]  ME: Firmware Init Complete      : YES
[DEBUG]  ME: Boot Options Present        : NO
[DEBUG]  ME: Update In Progress          : NO
[DEBUG]  ME: D0i3 Support                : YES
[DEBUG]  ME: Low Power State Enabled     : NO
[DEBUG]  ME: CPU Replaced                : YES
[DEBUG]  ME: CPU Replacement Valid       : YES
[DEBUG]  ME: Current Working State       : 5
[DEBUG]  ME: Current Operation State     : 1
[DEBUG]  ME: Current Operation Mode      : 0
[DEBUG]  ME: Error Code                  : 0
[DEBUG]  ME: CPU Debug Disabled          : YES
[DEBUG]  ME: TXT Support                 : NO
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x36b00 size 0x3420 in mcache @0x76c2d1f8
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 76b35000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  SCI is IRQ 9, GSI 9
[DEBUG]  ACPI:    * FACP
[DEBUG]  ACPI: added table 1/32, length now 44
[DEBUG]  Found 1 CPU(s) with 2/2 physical/logical core(s) each.
[DEBUG]  PCI space above 4GB MMIO is at 0x180400000, len = 0x7e7fc00000
[DEBUG]  Empty min sleep state array returned
[INFO ]  Returning default LPI constraint package
[INFO ]  \_SB.PCI0.PEPD: Intel Power Engine Plug-in
[INFO ]  \_SB.DPTF: Intel DPTF at GENERIC: 0.0
[INFO ]  \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ]  \_SB.PCI0.I2C4.DLG7: Dialog Semiconductor DA7219 Audio Codec address 01ah irq 0
[INFO ]  \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
[INFO ]  PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
[INFO ]  PS2K: Passing 80 keymaps to kernel
[INFO ]  PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
[INFO ]  \_SB.PCI0.HDAS.MAXM: Maxim Integrated 98357A Amplifier
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port at USB2 port 1
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS03: Left Type-A Port at USB2 port 2
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS04: Right Type-A Port at USB2 port 3
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS06: UFCamera at USB2 port 5
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS08: Bluetooth at USB2 port 7
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port at USB3 port 1
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS04: LTE at USB3 port 3
[DEBUG]  ACPI:    * SSDT
[DEBUG]  ACPI: added table 2/32, length now 52
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 60
[DEBUG]  TPM2 log created at 0x76b25000
[DEBUG]  ACPI:    * TPM2
[DEBUG]  ACPI: added table 4/32, length now 68
[DEBUG]  ACPI:    * LPIT
[DEBUG]  ACPI: added table 5/32, length now 76
[DEBUG]  IOAPIC: 120 interrupts
[DEBUG]  SCI is IRQ 9, GSI 9
[DEBUG]  ACPI:    * APIC
[DEBUG]  ACPI: added table 6/32, length now 84
[DEBUG]  current = 76b3a950
[DEBUG]  ACPI:    * DMAR
[DEBUG]  ACPI: added table 7/32, length now 92
[DEBUG]  ACPI: added table 8/32, length now 100
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 9/32, length now 108
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 23184 bytes.
[DEBUG]  smbios_write_tables: 76b1d000
[DEBUG]  BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-4.22.2-5-g822782a1001'
[INFO ]  Couldn't obtain OEM name from CBI
[INFO ]  Create SMBIOS type 16
[INFO ]  Create SMBIOS type 17
[INFO ]  Create SMBIOS type 20
[INFO ]  GENERIC: 0.0 (WIFI Device)
[DEBUG]  SMBIOS tables: 867 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum f928
[DEBUG]  Writing coreboot table at 0x76b59000
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG]   3. 0000000000100000-0000000076b1cfff: RAM
[DEBUG]   4. 0000000076b1d000-0000000076bc5fff: CONFIGURATION TABLES
[DEBUG]   5. 0000000076bc6000-0000000076c1dfff: RAMSTAGE
[DEBUG]   6. 0000000076c1e000-0000000076ffffff: CONFIGURATION TABLES
[DEBUG]   7. 0000000077000000-000000007fbfffff: RESERVED
[DEBUG]   8. 00000000c0000000-00000000cfffffff: RESERVED
[DEBUG]   9. 00000000fb000000-00000000fb000fff: RESERVED
[DEBUG]  10. 00000000fe000000-00000000fe00ffff: RESERVED
[DEBUG]  11. 00000000fe0b0000-00000000fe0bffff: RESERVED
[DEBUG]  12. 00000000fea80000-00000000fea87fff: RESERVED
[DEBUG]  13. 00000000fed80000-00000000fed83fff: RESERVED
[DEBUG]  14. 00000000fed90000-00000000fed92fff: RESERVED
[DEBUG]  15. 00000000feda0000-00000000feda1fff: RESERVED
[DEBUG]  16. 00000000ff000000-00000000ffffffff: RESERVED
[DEBUG]  17. 0000000100000000-00000001803fffff: RAM
[INFO ]  Board ID: 5
[INFO ]  FW config: 0x60000040000
[DEBUG]  Wrote coreboot table at: 0x76b59000, 0x584 bytes, checksum c7a7
[DEBUG]  coreboot table: 1436 bytes.
[DEBUG]  IMD ROOT    0. 0x76fff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x76ffe000 0x00001000
[DEBUG]  FSP MEMORY  2. 0x76c4e000 0x003b0000
[DEBUG]  CONSOLE     3. 0x76c2e000 0x00020000
[DEBUG]  RO MCACHE   4. 0x76c2d000 0x000003e0
[DEBUG]  TIME STAMP  5. 0x76c2c000 0x00000910
[DEBUG]  MEM INFO    6. 0x76c2b000 0x00000f48
[DEBUG]  AFTER CAR   7. 0x76c1e000 0x0000d000
[DEBUG]  RAMSTAGE    8. 0x76bc5000 0x00059000
[DEBUG]  REFCODE     9. 0x76b85000 0x00040000
[DEBUG]  SMM BACKUP 10. 0x76b75000 0x00010000
[DEBUG]  IGD OPREGION11. 0x76b71000 0x00003c43
[DEBUG]  SMM COMBUFFER12. 0x76b61000 0x00010000
[DEBUG]  COREBOOT   13. 0x76b59000 0x00008000
[DEBUG]  ACPI       14. 0x76b35000 0x00024000
[DEBUG]  TPM2 TCGLOG15. 0x76b25000 0x00010000
[DEBUG]  SMBIOS     16. 0x76b1d000 0x00008000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x76ffec00 0x00000400
[DEBUG]    FSP RUNTIME 1. 0x76ffebe0 0x00000004
[DEBUG]    VPD         2. 0x76ffeac0 0x00000110
[DEBUG]    FMAP        3. 0x76ffe920 0x00000188
[DEBUG]    CSE BP INFO 4. 0x76ffe8a0 0x00000068
[DEBUG]    CSE SPECIFIC INFO 5. 0x76ffe880 0x00000020
[DEBUG]    POWER STATE 6. 0x76ffe840 0x00000040
[DEBUG]    FSPM VERSION 7. 0x76ffe820 0x00000004
[DEBUG]    ROMSTAGE    8. 0x76ffe800 0x00000004
[DEBUG]    ROMSTG STCK 9. 0x76ffe740 0x000000a8
[DEBUG]    ACPI GNVS  10. 0x76ffe700 0x00000038
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 4 / 0 ms
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
[DEBUG]  0x0000000077000000 - 0x000000007fffffff size 0x09000000 type 0
[DEBUG]  0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
[DEBUG]  0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
[DEBUG]  0x0000000100000000 - 0x00000001803fffff size 0x80400000 type 6
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 6/5.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
[DEBUG]  MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
[DEBUG]  MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
[DEBUG]  MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[INFO ]  LAPIC 0x2 in XAPIC mode.
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
[DEBUG]  MTRR: TEMPORARY Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
[DEBUG]  0x0000000077000000 - 0x00000000feffffff size 0x88000000 type 0
[DEBUG]  0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
[DEBUG]  0x0000000100000000 - 0x00000001803fffff size 0x80400000 type 6
[DEBUG]  MTRR: default type WB/UC MTRR counts: 10/5.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
[DEBUG]  MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
[DEBUG]  MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
[DEBUG]  MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[INFO ]  CBFS: Found 'fallback/payload' @0x11de80 size 0x13ee4b in mcache @0x76c2d350
[DEBUG]  Checking segment from ROM address 0xffd220ac
[DEBUG]  Checking segment from ROM address 0xffd220c8
[DEBUG]  Loading segment from ROM address 0xffd220ac
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xffd220e4 filesize 0x13ee13
[DEBUG]  Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x000000000013ee13
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xffd220c8
[DEBUG]    Entry Point 0x0080168c
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 710 / 0 ms
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
[INFO ]  HECI: Sending End-of-Post
[INFO ]  CSE: EOP requested action: continue boot
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 8 / 0 ms
[DEBUG]  mp_park_aps done after 0 msecs.
[DEBUG]  Jumping to boot code at 0x0080168c(0x76b59000)

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 bootblock starting (log level: 7)...
[DEBUG]  CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz
[DEBUG]  CPU: ID 906c0, Jasperlake A0, ucode: 24000024
[DEBUG]  CPU: AES supported, TXT NOT supported, VT supported
[DEBUG]  MCH: device id 4e22 (rev 00) is Jasperlake SKU4-1
[DEBUG]  PCH: device id 4d87 (rev 01) is Jasperlake Super
[DEBUG]  IGD: device id 4e55 (rev 01) is Jasperlake GT4
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0xc04000.
[DEBUG]  FMAP: base = 0xff000000 size = 0x1000000 #areas = 8
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: mcache @0xfef31a00 built for 19 files, used 0x3e0 of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x10b60 in mcache @0xfef31a2c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 1 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 romstage starting (log level: 7)...
[DEBUG]  pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000
[DEBUG]  gpe0_sts[0]: 00000010 gpe0_en[0]: 00000000
[DEBUG]  gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
[DEBUG]  gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG]  gpe0_sts[3]: 00080040 gpe0_en[3]: 00000000
[DEBUG]  TCO_STS:   0000 0001
[DEBUG]  GEN_PMCON: d8a01a38 00002200
[DEBUG]  GBLRST_CAUSE: 00000040 00000000
[DEBUG]  prev_sleep_state 0
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'fspm.bin' @0x68dc0 size 0x79000 in mcache @0xfef31c98
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[DEBUG]  SPD INDEX = 0
[INFO ]  CBFS: Found 'spd.bin' @0x368c0 size 0x200 in mcache @0xfef31bd8
[INFO ]  SPD: module type is LPDDR4X
[INFO ]  SPD: module part number is                     
[INFO ]  SPD: banks 8, ranks 1, rows 16, columns 10, density 16384 Mb
[INFO ]  SPD: device width 16 bits, bus width 32 bits
[INFO ]  SPD: module size is 4096 MB (per channel)
[INFO ]  meminit_channels: DRAM half-populated
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x76fff000 254 entries.
[DEBUG]  IMD: root @ 0x76ffec00 62 entries.
[DEBUG]  FMAP: area RO_VPD found @ c00000 (16384 bytes)
[WARN ]  init_vpd_rdev: No RW_VPD FMAP section.
[DEBUG]  External stage cache:
[DEBUG]  IMD: root @ 0x7b3ff000 254 entries.
[DEBUG]  IMD: root @ 0x7b3fec00 62 entries.
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG]  MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG]  cse_lite: Number of partitions = 3
[DEBUG]  cse_lite: Current partition = RW
[DEBUG]  cse_lite: Next partition = RW
[DEBUG]  cse_lite: Flags = 0x7
[DEBUG]  cse_lite: RO version = 13.50.11.1304 (Status=0x0, Start=0x1000, End=0xebfff)
[DEBUG]  cse_lite: RW version = 13.50.11.1304 (Status=0x0, Start=0x140000, End=0x2c2fff)
[DEBUG]  1 DIMMs found
[DEBUG]  SMM Memory Map
[DEBUG]  SMRAM       : 0x7b000000 0x800000
[DEBUG]   Subregion 0: 0x7b000000 0x200000
[DEBUG]   Subregion 1: 0x7b200000 0x200000
[DEBUG]   Subregion 2: 0x7b400000 0x400000
[DEBUG]  top_of_ram = 0x77000000
[DEBUG]  Normal boot
[INFO ]  CBFS: Found 'fallback/postcar' @0x118740 size 0x56d4 in mcache @0xfef31d0c
[DEBUG]  Loading module at 0x76c1f000 with entry 0x76c1f031. filesize: 0x5348 memsize: 0xb698
[DEBUG]  Processing 211 relocs. Offset value of 0x74c1f000
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 2 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 postcar starting (log level: 7)...
[DEBUG]  Normal boot
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'fallback/ramstage' @0x15d40 size 0x1f5e8 in mcache @0x76c2d10c
[DEBUG]  Loading module at 0x76bc6000 with entry 0x76bc6000. filesize: 0x42ad0 memsize: 0x57ed0
[DEBUG]  Processing 4633 relocs. Offset value of 0x72bc6000
[DEBUG]  BS: postcar times (exec / console): total (unknown) / 0 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 ramstage starting (log level: 7)...
[DEBUG]  Normal boot
[INFO ]  FW_CONFIG value from CBI is 0x60000040000
[INFO ]  fw_config match found: AUDIO_AMP=UNPROVISIONED
[INFO ]  GENERIC: 0.0 disabled by fw_config
[DEBUG]  microcode: sig=0x906c0 pf=0x1 revision=0x24000024
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0x10c80 size 0x5000 in mcache @0x76c2d0ac
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CBFS: Found 'fsps.bin' @0xe1e00 size 0x36906 in mcache @0x76c2d2d8
[DEBUG]  Detected 2 core, 2 thread CPU.
[DEBUG]  Setting up SMI for CPU
[DEBUG]  IED base = 0x7b400000
[DEBUG]  IED size = 0x00400000
[INFO ]  Will perform SMM setup.
[INFO ]  CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  CPU: APIC: 00 enabled
[DEBUG]  CPU: APIC: 01 enabled
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 16 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 1 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x2 in XAPIC mode.
[INFO ]  AP: slot 1 apic_id 2, MCU rev: 0x24000024
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x198 memsize: 0x198
[DEBUG]  Processing 9 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x76be45cd
[DEBUG]  Installing permanent SMM handler to 0x7b000000
[DEBUG]  HANDLER      [0x7b1fc000-0x7b1ff6e8]

[DEBUG]  CPU 0
[DEBUG]    ss0        [0x7b1fbc00-0x7b1fc000]
[DEBUG]    stub0      [0x7b1f4000-0x7b1f4198]

[DEBUG]  CPU 1
[DEBUG]    ss1        [0x7b1fb800-0x7b1fbc00]
[DEBUG]    stub1      [0x7b1f3c00-0x7b1f3d98]

[DEBUG]  stacks       [0x7b000000-0x7b001000]
[DEBUG]  Loading module at 0x7b1fc000 with entry 0x7b1fca26. filesize: 0x3638 memsize: 0x36e8
[DEBUG]  Processing 182 relocs. Offset value of 0x7b1fc000
[DEBUG]  Loading module at 0x7b1f4000 with entry 0x7b1f4000. filesize: 0x198 memsize: 0x198
[DEBUG]  Processing 9 relocs. Offset value of 0x7b1f4000
[DEBUG]  smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x200000
[DEBUG]  SMM Module: placing smm entry code at 7b1f3c00,  cpu # 0x1
[DEBUG]  SMM Module: stub loaded at 7b1f4000. Will call 0x7b1fca26
[DEBUG]  Clearing SMI status registers
[DEBUG]  TCO_STS: INTRD_DET 
[DEBUG]  GPE0 STD STS: TCO_SCI 
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ec000, cpu = 0
[DEBUG]  In relocation handler: CPU 0
[DEBUG]  New SMBASE=0x7b1ec000 IEDBASE=0x7b400000
[DEBUG]  Writing SMRR. base = 0x7b000006, mask=0xff800c00
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ebc00, cpu = 1
[DEBUG]  In relocation handler: CPU 1
[DEBUG]  New SMBASE=0x7b1ebc00 IEDBASE=0x7b400000
[DEBUG]  Writing SMRR. base = 0x7b000006, mask=0xff800c00
[DEBUG]  Relocation complete.
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 906c0
[DEBUG]  CPU: family 06, model 9c, stepping 00
[DEBUG]  Clearing out pending MCEs
[INFO ]  Turbo is available but hidden
[INFO ]  Turbo is available and visible
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #1
[DEBUG]  CPU: vendor Intel device 906c0
[DEBUG]  CPU: family 06, model 9c, stepping 00
[DEBUG]  Clearing out pending MCEs
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CPU #1 initialized
[INFO ]  bsp_do_flight_plan done after 1 msecs.
[DEBUG]  CPU: frequency set to 2800 MHz
[DEBUG]  Enabling SMIs.
[DEBUG]  BS: BS_DEV_INIT_CHIPS entry times (exec / console): 41 / 0 ms
[INFO ]  Probing TPM: . done!
[INFO ]  TPM ready after 0 ms
[INFO ]  Connected to device vid:did:rid of 1ae0:0028:00
[INFO ]  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_A:0.5.215/cr50_v2.94_mp.294-221da5d8be
[INFO ]  Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
[INFO ]  Initialized TPM device CR50 revision 0
[INFO ]  CBFS: Found 'vbt.bin' @0x68880 size 0x4b4 in mcache @0x76c2d268
[INFO ]  Found a VBT of 7680 bytes
[DEBUG]  WEAK: src/soc/intel/jasperlake/fsp_params.c/mainboard_silicon_init_params called
[DEBUG]  Detected 2 core, 2 thread CPU.
[DEBUG]  Detected 2 core, 2 thread CPU.
[INFO ]  FSPS returned 0
[DEBUG]  Display FSP Version Info HOB
[DEBUG]  Reference Code - CPU = 8.7.22.30
[DEBUG]  uCode Version = 24.0.0.24
[DEBUG]  TXT ACM version = ff.ff.ff.ffff
[DEBUG]  Reference Code - ME = 8.7.22.30
[DEBUG]  MEBx version = 0.0.0.0
[DEBUG]  ME Firmware Version = Lite SKU
[DEBUG]  Reference Code - PCH = 8.7.22.30
[DEBUG]  PCH-CRID Status = Disabled
[DEBUG]  PCH-CRID Original Value = ff.ff.ff.ffff
[DEBUG]  PCH-CRID New Value = ff.ff.ff.ffff
[DEBUG]  OPROM - RST - RAID = ff.ff.ff.ffff
[DEBUG]  PCH Hsio Version = 4.0.0.0
[DEBUG]  Reference Code - SA - System Agent = 8.7.22.30
[DEBUG]  Reference Code - MRC = 0.0.4.68
[DEBUG]  SA - PCIe Version = 8.7.22.30
[DEBUG]  SA-CRID Status = Disabled
[DEBUG]  SA-CRID Original Value = 0.0.0.0
[DEBUG]  SA-CRID New Value = 0.0.0.0
[DEBUG]  OPROM - VBIOS = ff.ff.ff.ffff
[DEBUG]  IO Manageability Engine FW Version = ff.ff.ff.ffff
[DEBUG]  PHY Build Version = ff.ff.ff.ffff
[DEBUG]  Thunderbolt(TM) FW Version = ff.ff.ff.ffff
[DEBUG]  System Agent Manageability Engine FW Version = ff.ff.ff.ffff
[DEBUG]  BS: BS_DEV_INIT_CHIPS run times (exec / console): 151 / 0 ms
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 0000 enabled
[DEBUG]  DOMAIN: 0000 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 00
[DEBUG]  PCI: 00:00.0 [8086/4e22] enabled
[DEBUG]  PCI: 00:02.0 [8086/4e55] enabled
[DEBUG]  PCI: 00:04.0 [8086/4e03] enabled
[DEBUG]  PCI: 00:08.0 [8086/4e11] enabled
[DEBUG]  PCI: 00:14.0 [8086/4ded] enabled
[DEBUG]  PCI: 00:14.2 [8086/4def] disabled
[DEBUG]  PCI: 00:14.3 [8086/4df0] enabled
[DEBUG]  PCI: 00:14.5 [8086/4df8] enabled
[DEBUG]  PCI: 00:15.0 [8086/4de8] enabled
[DEBUG]  PCI: 00:15.1 [8086/4de9] enabled
[DEBUG]  PCI: 00:15.2 [8086/4dea] enabled
[DEBUG]  PCI: 00:15.3 [8086/4deb] enabled
[DEBUG]  PCI: 00:16.0 [8086/4de0] enabled
[DEBUG]  PCI: 00:19.0 [8086/4dc5] enabled
[DEBUG]  PCI: 00:19.2 [8086/4dc7] enabled
[DEBUG]  PCI: 00:1a.0 [8086/4dc4] enabled
[DEBUG]  PCI: 00:1e.0 [8086/4da8] disabled
[DEBUG]  PCI: 00:1e.2 [8086/4daa] enabled
[DEBUG]  PCI: 00:1f.0 [8086/4d87] enabled
[INFO ]  PCI: Static device PCI: 00:1f.1 not found, disabling it.
[DEBUG]  RTC Init
[INFO ]  Set power on after power failure.
[DEBUG]  Disabling Deep S3
[DEBUG]  Disabling Deep S3
[DEBUG]  Disabling Deep S4
[DEBUG]  Disabling Deep S4
[DEBUG]  Disabling Deep S5
[DEBUG]  Disabling Deep S5
[DEBUG]  PCI: 00:1f.2 [0000/0000] hidden
[DEBUG]  PCI: 00:1f.3 [8086/4dc8] enabled
[DEBUG]  PCI: 00:1f.5 [8086/4da4] enabled
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:12.6
[WARN ]  PCI: 00:05.0
[WARN ]  PCI: 00:09.0
[WARN ]  PCI: 00:14.1
[WARN ]  PCI: 00:16.1
[WARN ]  PCI: 00:16.4
[WARN ]  PCI: 00:16.5
[WARN ]  PCI: 00:17.0
[WARN ]  PCI: 00:19.1
[WARN ]  PCI: 00:1e.1
[WARN ]  PCI: 00:1e.3
[WARN ]  PCI: 00:1f.1
[WARN ]  PCI: 00:1f.4
[WARN ]  PCI: 00:1f.7
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:02.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:02.0 finished in 0 msecs
[DEBUG]  PCI: 00:04.0 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  bus: PCI: 00:04.0[0]->scan_bus: bus PCI: 00:04.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.0 scanning...
[DEBUG]  USB0 port 0 enabled
[DEBUG]  USB0 port 0 scanning...
[DEBUG]  USB2 port 0 enabled
[DEBUG]  USB2 port 1 enabled
[DEBUG]  USB2 port 2 enabled
[DEBUG]  USB2 port 3 enabled
[DEBUG]  USB2 port 4 disabled
[DEBUG]  USB2 port 5 enabled
[DEBUG]  USB2 port 6 disabled
[DEBUG]  USB2 port 7 enabled
[DEBUG]  USB3 port 0 enabled
[DEBUG]  USB3 port 1 enabled
[DEBUG]  USB3 port 2 enabled
[DEBUG]  USB3 port 3 enabled
[DEBUG]  USB2 port 0 scanning...
[DEBUG]  scan_bus: bus USB2 port 0 finished in 0 msecs
[DEBUG]  USB2 port 1 scanning...
[DEBUG]  scan_bus: bus USB2 port 1 finished in 0 msecs
[DEBUG]  USB2 port 2 scanning...
[DEBUG]  scan_bus: bus USB2 port 2 finished in 0 msecs
[DEBUG]  USB2 port 3 scanning...
[DEBUG]  scan_bus: bus USB2 port 3 finished in 0 msecs
[DEBUG]  USB2 port 5 scanning...
[DEBUG]  scan_bus: bus USB2 port 5 finished in 0 msecs
[DEBUG]  USB2 port 7 scanning...
[DEBUG]  scan_bus: bus USB2 port 7 finished in 0 msecs
[DEBUG]  USB3 port 0 scanning...
[DEBUG]  scan_bus: bus USB3 port 0 finished in 0 msecs
[DEBUG]  USB3 port 1 scanning...
[DEBUG]  scan_bus: bus USB3 port 1 finished in 0 msecs
[DEBUG]  USB3 port 2 scanning...
[DEBUG]  scan_bus: bus USB3 port 2 finished in 0 msecs
[DEBUG]  USB3 port 3 scanning...
[DEBUG]  scan_bus: bus USB3 port 3 finished in 0 msecs
[DEBUG]  scan_bus: bus USB0 port 0 finished in 0 msecs
[DEBUG]  scan_bus: bus PCI: 00:14.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.3 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:14.3 finished in 0 msecs
[DEBUG]  PCI: 00:15.0 scanning...
[DEBUG]  I2C: 00:15 enabled
[DEBUG]  I2C: 00:40 enabled
[DEBUG]  scan_bus: bus PCI: 00:15.0 finished in 0 msecs
[DEBUG]  PCI: 00:15.1 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.1 finished in 0 msecs
[DEBUG]  PCI: 00:15.2 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.2 finished in 0 msecs
[DEBUG]  PCI: 00:15.3 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.3 finished in 0 msecs
[DEBUG]  PCI: 00:19.0 scanning...
[DEBUG]  I2C: 00:1a enabled
[DEBUG]  scan_bus: bus PCI: 00:19.0 finished in 0 msecs
[DEBUG]  PCI: 00:1e.2 scanning...
[DEBUG]  SPI: 00 enabled
[DEBUG]  bus: PCI: 00:1e.2[0]->scan_bus: bus PCI: 00:1e.2 finished in 0 msecs
[DEBUG]  PCI: 00:1f.0 scanning...
[DEBUG]  PNP: 0c09.0 enabled
[DEBUG]  PNP: 0c09.0 scanning...
[DEBUG]  scan_bus: bus PNP: 0c09.0 finished in 0 msecs
[DEBUG]  scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
[DEBUG]  PCI: 00:1f.3 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  GENERIC: 0.0 disabled
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
[DEBUG]  scan_bus: bus DOMAIN: 0000 finished in 1 msecs
[DEBUG]  scan_bus: bus Root Device finished in 1 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms
[INFO ]  MRC: Could not find region 'UNIFIED_MRC_CACHE'
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[INFO ]  MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
[DEBUG]  found VGA at PCI: 00:02.0
[DEBUG]  Setting up VGA for PCI: 00:02.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[DEBUG]  SA MMIO resource: PCIEXBAR ->  base = 0xc0000000, size = 0x10000000
[DEBUG]  SA MMIO resource: MCHBAR   ->  base = 0xfea80000, size = 0x00008000
[DEBUG]  SA MMIO resource: DMIBAR   ->  base = 0xfeda0000, size = 0x00001000
[DEBUG]  SA MMIO resource: EPBAR    ->  base = 0xfeda1000, size = 0x00001000
[DEBUG]  SA MMIO resource: REGBAR   ->  base = 0xfb000000, size = 0x00001000
[DEBUG]  SA MMIO resource: EDRAMBAR ->  base = 0xfed80000, size = 0x00004000
[DEBUG]  SA MMIO resource: GFXVTBAR ->  base = 0xfed90000, size = 0x00001000
[DEBUG]  SA MMIO resource: IPUVTBAR ->  base = 0xfed92000, size = 0x00001000
[DEBUG]  SA MMIO resource: VTVC0BAR ->  base = 0xfed91000, size = 0x00001000
[INFO ]  Available memory above 4GB: 2052M
[INFO ]  Done reading resources.
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 1 (relative placement) ===
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 84 base 00000800 limit 000008ff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 88 base 00000200 limit 0000020f io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 8c base 00000900 limit 000009ff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 90 base 00000080 limit 0000008f io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 1000, Size: 800, Tag: 100
[INFO ]   * Base: 1900, Size: e700, Tag: 100
[DEBUG]    PCI: 00:02.0 20 *  [0x1000 - 0x103f] limit: 103f io
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 0000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff
[DEBUG]  DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 01 base fea80000 limit fea87fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 08 base fed91000 limit fed91fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0a base 000c0000 limit 76ffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0b base 77000000 limit 7fbfffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0c base 100000000 limit 1803fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0d base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0e base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:19.2 10 base fe032000 limit fe032fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 98 base fe0b0000 limit fe0bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.2 10 base fe000000 limit fe00ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.5 00 base ff000000 limit ffffffff mem (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 7fc00000, Size: 40400000, Tag: 200
[INFO ]   * Base: d0000000, Size: 10000000, Tag: 200
[INFO ]   * Base: 180400000, Size: 7e7fc00000, Tag: 200
[DEBUG]    PCI: 00:02.0 18 *  [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
[DEBUG]    PCI: 00:02.0 10 *  [0x90000000 - 0x90ffffff] limit: 90ffffff mem
[DEBUG]    PCI: 00:1f.3 20 *  [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
[DEBUG]    PCI: 00:04.0 10 *  [0x7fd00000 - 0x7fd0ffff] limit: 7fd0ffff mem
[DEBUG]    PCI: 00:14.0 10 *  [0x7fd10000 - 0x7fd1ffff] limit: 7fd1ffff mem
[DEBUG]    PCI: 00:14.3 10 *  [0x7fd20000 - 0x7fd23fff] limit: 7fd23fff mem
[DEBUG]    PCI: 00:1f.3 10 *  [0x7fd24000 - 0x7fd27fff] limit: 7fd27fff mem
[DEBUG]    PCI: 00:08.0 10 *  [0x7fd28000 - 0x7fd28fff] limit: 7fd28fff mem
[DEBUG]    PCI: 00:14.5 10 *  [0x7fd29000 - 0x7fd29fff] limit: 7fd29fff mem
[DEBUG]    PCI: 00:15.0 10 *  [0x7fd2a000 - 0x7fd2afff] limit: 7fd2afff mem
[DEBUG]    PCI: 00:15.1 10 *  [0x7fd2b000 - 0x7fd2bfff] limit: 7fd2bfff mem
[DEBUG]    PCI: 00:15.2 10 *  [0x7fd2c000 - 0x7fd2cfff] limit: 7fd2cfff mem
[DEBUG]    PCI: 00:15.3 10 *  [0x7fd2d000 - 0x7fd2dfff] limit: 7fd2dfff mem
[DEBUG]    PCI: 00:16.0 10 *  [0x7fd2e000 - 0x7fd2efff] limit: 7fd2efff mem
[DEBUG]    PCI: 00:19.0 10 *  [0x7fd2f000 - 0x7fd2ffff] limit: 7fd2ffff mem
[DEBUG]    PCI: 00:19.2 18 *  [0x7fd30000 - 0x7fd30fff] limit: 7fd30fff mem
[DEBUG]    PCI: 00:1a.0 10 *  [0x7fd31000 - 0x7fd31fff] limit: 7fd31fff mem
[DEBUG]    PCI: 00:1e.2 10 *  [0x7fd32000 - 0x7fd32fff] limit: 7fd32fff mem
[DEBUG]    PCI: 00:1f.5 10 *  [0x7fd33000 - 0x7fd33fff] limit: 7fd33fff mem
[DEBUG]  DOMAIN: 0000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff done
[DEBUG]  DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[DEBUG]  PCI: 00:02.0 10 <- [0x0000000090000000 - 0x0000000090ffffff] size 0x01000000 gran 0x18 mem64
[DEBUG]  PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG]  PCI: 00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
[DEBUG]  PCI: 00:04.0 10 <- [0x000000007fd00000 - 0x000000007fd0ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:08.0 10 <- [0x000000007fd28000 - 0x000000007fd28fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:14.0 10 <- [0x000000007fd10000 - 0x000000007fd1ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:14.3 10 <- [0x000000007fd20000 - 0x000000007fd23fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:14.5 10 <- [0x000000007fd29000 - 0x000000007fd29fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.0 10 <- [0x000000007fd2a000 - 0x000000007fd2afff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.1 10 <- [0x000000007fd2b000 - 0x000000007fd2bfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.2 10 <- [0x000000007fd2c000 - 0x000000007fd2cfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.3 10 <- [0x000000007fd2d000 - 0x000000007fd2dfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:16.0 10 <- [0x000000007fd2e000 - 0x000000007fd2efff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:19.0 10 <- [0x000000007fd2f000 - 0x000000007fd2ffff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:19.2 18 <- [0x000000007fd30000 - 0x000000007fd30fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1a.0 10 <- [0x000000007fd31000 - 0x000000007fd31fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1e.2 10 <- [0x000000007fd32000 - 0x000000007fd32fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1f.3 10 <- [0x000000007fd24000 - 0x000000007fd27fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:1f.3 20 <- [0x000000007fc00000 - 0x000000007fcfffff] size 0x00100000 gran 0x14 mem64
[DEBUG]  PCI: 00:1f.5 10 <- [0x000000007fd33000 - 0x000000007fd33fff] size 0x00001000 gran 0x0c mem
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00.0 subsystem <- 8086/4e22
[DEBUG]  PCI: 00:00.0 cmd <- 06
[DEBUG]  PCI: 00:02.0 subsystem <- 8086/4e55
[DEBUG]  PCI: 00:02.0 cmd <- 03
[DEBUG]  PCI: 00:04.0 subsystem <- 8086/4e03
[DEBUG]  PCI: 00:04.0 cmd <- 02
[DEBUG]  PCI: 00:08.0 subsystem <- 8086/4e11
[DEBUG]  PCI: 00:08.0 cmd <- 06
[DEBUG]  PCI: 00:14.0 subsystem <- 8086/4ded
[DEBUG]  PCI: 00:14.0 cmd <- 02
[DEBUG]  PCI: 00:14.3 subsystem <- 8086/4df0
[DEBUG]  PCI: 00:14.3 cmd <- 02
[DEBUG]  PCI: 00:14.5 subsystem <- 8086/4df8
[DEBUG]  PCI: 00:14.5 cmd <- 06
[DEBUG]  PCI: 00:15.0 subsystem <- 8086/4de8
[DEBUG]  PCI: 00:15.0 cmd <- 02
[DEBUG]  PCI: 00:15.1 subsystem <- 8086/4de9
[DEBUG]  PCI: 00:15.1 cmd <- 02
[DEBUG]  PCI: 00:15.2 subsystem <- 8086/4dea
[DEBUG]  PCI: 00:15.2 cmd <- 02
[DEBUG]  PCI: 00:15.3 subsystem <- 8086/4deb
[DEBUG]  PCI: 00:15.3 cmd <- 02
[DEBUG]  PCI: 00:16.0 subsystem <- 8086/4de0
[DEBUG]  PCI: 00:16.0 cmd <- 02
[DEBUG]  PCI: 00:19.0 subsystem <- 8086/4dc5
[DEBUG]  PCI: 00:19.0 cmd <- 02
[DEBUG]  PCI: 00:19.2 subsystem <- 8086/4dc7
[DEBUG]  PCI: 00:19.2 cmd <- 06
[DEBUG]  PCI: 00:1a.0 subsystem <- 8086/4dc4
[DEBUG]  PCI: 00:1a.0 cmd <- 06
[DEBUG]  PCI: 00:1e.2 subsystem <- 8086/4daa
[DEBUG]  PCI: 00:1e.2 cmd <- 06
[DEBUG]  PCI: 00:1f.0 subsystem <- 8086/4d87
[DEBUG]  PCI: 00:1f.0 cmd <- 407
[DEBUG]  PCI: 00:1f.3 subsystem <- 8086/4dc8
[DEBUG]  PCI: 00:1f.3 cmd <- 02
[DEBUG]  PCI: 00:1f.5 subsystem <- 8086/4da4
[DEBUG]  PCI: 00:1f.5 cmd <- 406
[INFO ]  done.
[INFO ]  Initializing devices...
[DEBUG]  Root Device init
[INFO ]  mainboard: EC init
[DEBUG]  Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG]  Chrome EC: UHEPI supported
[DEBUG]  Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
[DEBUG]  Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
[DEBUG]  Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001009105e
[DEBUG]  Chrome EC: Set WAKE mask to 0x0000000000000000
[DEBUG]  Root Device init finished in 1 msecs
[DEBUG]  PCI: 00:00.0 init
[INFO ]  CPU TDP = 6 Watts
[INFO ]  CPU PL1 = 6 Watts
[INFO ]  CPU PL2 = 20 Watts
[DEBUG]  PCI: 00:00.0 init finished in 1 msecs
[DEBUG]  PCI: 00:02.0 init
[INFO ]  GMA: Found VBT in CBFS
[INFO ]  GMA: Found valid VBT in CBFS
[INFO ]  framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32
[INFO ]                     x_res x y_res: 1366 x 768, size: 4227072 at 0x80000000
[DEBUG]  PCI: 00:02.0 init finished in 0 msecs
[DEBUG]  PCI: 00:08.0 init
[DEBUG]  PCI: 00:08.0 init finished in 0 msecs
[DEBUG]  PCI: 00:14.0 init
[DEBUG]  XHCI: Updated LFPS sampling OFF time to 9 ms
[DEBUG]  PCI: 00:14.0 init finished in 0 msecs
[DEBUG]  PCI: 00:15.0 init
[DEBUG]  I2C bus 0 version 0x3230302a
[INFO ]  DW I2C bus 0 at 0x7fd2a000 (400 KHz)
[DEBUG]  PCI: 00:15.0 init finished in 0 msecs
[DEBUG]  PCI: 00:15.1 init
[DEBUG]  I2C bus 1 version 0x3230302a
[INFO ]  DW I2C bus 1 at 0x7fd2b000 (400 KHz)
[DEBUG]  PCI: 00:15.1 init finished in 0 msecs
[DEBUG]  PCI: 00:15.2 init
[DEBUG]  I2C bus 2 version 0x3230302a
[INFO ]  DW I2C bus 2 at 0x7fd2c000 (400 KHz)
[DEBUG]  PCI: 00:15.2 init finished in 0 msecs
[DEBUG]  PCI: 00:15.3 init
[DEBUG]  I2C bus 3 version 0x3230302a
[INFO ]  DW I2C bus 3 at 0x7fd2d000 (400 KHz)
[DEBUG]  PCI: 00:15.3 init finished in 0 msecs
[DEBUG]  PCI: 00:16.0 init
[DEBUG]  PCI: 00:16.0 init finished in 0 msecs
[DEBUG]  PCI: 00:19.0 init
[DEBUG]  I2C bus 4 version 0x3230302a
[INFO ]  DW I2C bus 4 at 0x7fd2f000 (400 KHz)
[DEBUG]  PCI: 00:19.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1a.0 init
[DEBUG]  PCI: 00:1a.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1f.0 init
[DEBUG]  IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: ID = 0x00
[DEBUG]  IOAPIC: 120 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[DEBUG]  PCI: 00:1f.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1f.2 init
[DEBUG]  apm_control: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  PCI: 00:1f.2 init finished in 2 msecs
[DEBUG]  PCI: 00:1f.3 init
[DEBUG]  PCI: 00:1f.3 init finished in 0 msecs
[DEBUG]  PNP: 0c09.0 init
[DEBUG]  Google Chrome EC: Initializing
[DEBUG]  Google Chrome EC uptime: 223.219 seconds
[DEBUG]  Google Chrome AP resets since EC boot: 1
[DEBUG]  Google Chrome most recent AP reset causes:
[DEBUG]     0.395: 32775 shutdown: entering G3
[DEBUG]  Google Chrome EC reset flags at last EC boot: reset-pin | power-on | sysjump
[DEBUG]  Google Chrome EC: version:
[DEBUG]     ro: sasukette_v2.0.10540-df222fb19
[DEBUG]     rw: sasukette_v2.0.22514-05e2f7f803
[DEBUG]    running image: 2
[INFO ]  CBFS: Found 'ecrw.hash' @0x68800 size 0x20 in mcache @0x76c2d244
[DEBUG]  ChromeEC SW Sync: Expected hash: 01f3b2044c741b45d57c535f5c68daf0c59cb910ffd1d76a27516c706880a0ec
[DEBUG]  ChromeEC: Getting hash:
[DEBUG]  ChromeEC: No valid hash (status=0 size=0). Compute one...
[DEBUG]  ChromeEC: Starting EC hash:
[DEBUG]  ChromeEC SW Sync: current EC_RW hash: b14cca7d78a45093c344d2ae3d6e5738ae57d21a595b435dbf55586854339b51
[DEBUG]  ChromeEC SW Sync: updating EC_RW...
[INFO ]  CBFS: Found 'ecrw' @0x39f80 size 0x2e85c in mcache @0x76c2d224
[DEBUG]  Getting EC region info
[ERROR]  ChromeEC SW Sync: Failed to update EC_RW.
[ERROR]  ChromeEC: EC SW SYNC FAILED
[DEBUG]  PNP: 0c09.0 init finished in 641 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 647 / 0 ms
[DEBUG]  FMAP: area SMMSTORE found @ bc0000 (262144 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG]  smm store: 4 # blocks with size 0x10000
[INFO ]  SMMSTORE: Setting up SMI handler
[INFO ]  tlcl_send_startup: Startup return code is 0x0
[INFO ]  TPM: setup succeeded
[DEBUG]  BS: BS_DEV_INIT exit times (exec / console): 50 / 0 ms
[INFO ]  Finalize devices...
[DEBUG]  PCI: 00:02.0 final
[DEBUG]  PCI: 00:16.0 final
[DEBUG]  CSE RW Firmware Version: 0.0.0.0
[DEBUG]  PCI: 00:1f.2 final
[INFO ]  Devices finalized
[DEBUG]  ME: HFSTS1                      : 0x90000245
[DEBUG]  ME: HFSTS2                      : 0x86100126
[DEBUG]  ME: HFSTS3                      : 0x00000050
[DEBUG]  ME: HFSTS4                      : 0x00004000
[DEBUG]  ME: HFSTS5                      : 0x00000000
[DEBUG]  ME: HFSTS6                      : 0x40400006
[DEBUG]  ME: Manufacturing Mode          : NO
[DEBUG]  ME: SPI Protection Mode Enabled : YES
[DEBUG]  ME: FW Partition Table          : OK
[DEBUG]  ME: Bringup Loader Failure      : NO
[DEBUG]  ME: Firmware Init Complete      : YES
[DEBUG]  ME: Boot Options Present        : NO
[DEBUG]  ME: Update In Progress          : NO
[DEBUG]  ME: D0i3 Support                : YES
[DEBUG]  ME: Low Power State Enabled     : NO
[DEBUG]  ME: CPU Replaced                : NO
[DEBUG]  ME: CPU Replacement Valid       : YES
[DEBUG]  ME: Current Working State       : 5
[DEBUG]  ME: Current Operation State     : 1
[DEBUG]  ME: Current Operation Mode      : 0
[DEBUG]  ME: Error Code                  : 0
[DEBUG]  ME: CPU Debug Disabled          : YES
[DEBUG]  ME: TXT Support                 : NO
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x36b00 size 0x3420 in mcache @0x76c2d1f8
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 76b35000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  SCI is IRQ 9, GSI 9
[DEBUG]  ACPI:    * FACP
[DEBUG]  ACPI: added table 1/32, length now 44
[DEBUG]  Found 1 CPU(s) with 2/2 physical/logical core(s) each.
[DEBUG]  PCI space above 4GB MMIO is at 0x180400000, len = 0x7e7fc00000
[DEBUG]  Empty min sleep state array returned
[INFO ]  Returning default LPI constraint package
[INFO ]  \_SB.PCI0.PEPD: Intel Power Engine Plug-in
[INFO ]  \_SB.DPTF: Intel DPTF at GENERIC: 0.0
[INFO ]  \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ]  \_SB.PCI0.I2C4.DLG7: Dialog Semiconductor DA7219 Audio Codec address 01ah irq 0
[INFO ]  \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
[INFO ]  PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
[INFO ]  PS2K: Passing 80 keymaps to kernel
[INFO ]  PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
[INFO ]  \_SB.PCI0.HDAS.MAXM: Maxim Integrated 98357A Amplifier
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port at USB2 port 1
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS03: Left Type-A Port at USB2 port 2
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS04: Right Type-A Port at USB2 port 3
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS06: UFCamera at USB2 port 5
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS08: Bluetooth at USB2 port 7
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port at USB3 port 1
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS04: LTE at USB3 port 3
[DEBUG]  ACPI:    * SSDT
[DEBUG]  ACPI: added table 2/32, length now 52
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 60
[DEBUG]  TPM2 log created at 0x76b25000
[DEBUG]  ACPI:    * TPM2
[DEBUG]  ACPI: added table 4/32, length now 68
[DEBUG]  ACPI:    * LPIT
[DEBUG]  ACPI: added table 5/32, length now 76
[DEBUG]  IOAPIC: 120 interrupts
[DEBUG]  SCI is IRQ 9, GSI 9
[DEBUG]  ACPI:    * APIC
[DEBUG]  ACPI: added table 6/32, length now 84
[DEBUG]  current = 76b3a950
[DEBUG]  ACPI:    * DMAR
[DEBUG]  ACPI: added table 7/32, length now 92
[DEBUG]  ACPI: added table 8/32, length now 100
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 9/32, length now 108
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 23184 bytes.
[DEBUG]  smbios_write_tables: 76b1d000
[DEBUG]  BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-4.22.2-5-g822782a1001'
[INFO ]  Couldn't obtain OEM name from CBI
[INFO ]  Create SMBIOS type 16
[INFO ]  Create SMBIOS type 17
[INFO ]  Create SMBIOS type 20
[INFO ]  GENERIC: 0.0 (WIFI Device)
[DEBUG]  SMBIOS tables: 867 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum f928
[DEBUG]  Writing coreboot table at 0x76b59000
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG]   3. 0000000000100000-0000000076b1cfff: RAM
[DEBUG]   4. 0000000076b1d000-0000000076bc5fff: CONFIGURATION TABLES
[DEBUG]   5. 0000000076bc6000-0000000076c1dfff: RAMSTAGE
[DEBUG]   6. 0000000076c1e000-0000000076ffffff: CONFIGURATION TABLES
[DEBUG]   7. 0000000077000000-000000007fbfffff: RESERVED
[DEBUG]   8. 00000000c0000000-00000000cfffffff: RESERVED
[DEBUG]   9. 00000000fb000000-00000000fb000fff: RESERVED
[DEBUG]  10. 00000000fe000000-00000000fe00ffff: RESERVED
[DEBUG]  11. 00000000fe0b0000-00000000fe0bffff: RESERVED
[DEBUG]  12. 00000000fea80000-00000000fea87fff: RESERVED
[DEBUG]  13. 00000000fed80000-00000000fed83fff: RESERVED
[DEBUG]  14. 00000000fed90000-00000000fed92fff: RESERVED
[DEBUG]  15. 00000000feda0000-00000000feda1fff: RESERVED
[DEBUG]  16. 00000000ff000000-00000000ffffffff: RESERVED
[DEBUG]  17. 0000000100000000-00000001803fffff: RAM
[INFO ]  Board ID: 5
[INFO ]  FW config: 0x60000040000
[DEBUG]  Wrote coreboot table at: 0x76b59000, 0x584 bytes, checksum c7a7
[DEBUG]  coreboot table: 1436 bytes.
[DEBUG]  IMD ROOT    0. 0x76fff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x76ffe000 0x00001000
[DEBUG]  FSP MEMORY  2. 0x76c4e000 0x003b0000
[DEBUG]  CONSOLE     3. 0x76c2e000 0x00020000
[DEBUG]  RO MCACHE   4. 0x76c2d000 0x000003e0
[DEBUG]  TIME STAMP  5. 0x76c2c000 0x00000910
[DEBUG]  MEM INFO    6. 0x76c2b000 0x00000f48
[DEBUG]  AFTER CAR   7. 0x76c1e000 0x0000d000
[DEBUG]  RAMSTAGE    8. 0x76bc5000 0x00059000
[DEBUG]  REFCODE     9. 0x76b85000 0x00040000
[DEBUG]  SMM BACKUP 10. 0x76b75000 0x00010000
[DEBUG]  IGD OPREGION11. 0x76b71000 0x00003c43
[DEBUG]  SMM COMBUFFER12. 0x76b61000 0x00010000
[DEBUG]  COREBOOT   13. 0x76b59000 0x00008000
[DEBUG]  ACPI       14. 0x76b35000 0x00024000
[DEBUG]  TPM2 TCGLOG15. 0x76b25000 0x00010000
[DEBUG]  SMBIOS     16. 0x76b1d000 0x00008000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x76ffec00 0x00000400
[DEBUG]    FSP RUNTIME 1. 0x76ffebe0 0x00000004
[DEBUG]    VPD         2. 0x76ffeac0 0x00000110
[DEBUG]    FMAP        3. 0x76ffe920 0x00000188
[DEBUG]    CSE BP INFO 4. 0x76ffe8a0 0x00000068
[DEBUG]    CSE SPECIFIC INFO 5. 0x76ffe880 0x00000020
[DEBUG]    POWER STATE 6. 0x76ffe840 0x00000040
[DEBUG]    FSPM VERSION 7. 0x76ffe820 0x00000004
[DEBUG]    ROMSTAGE    8. 0x76ffe800 0x00000004
[DEBUG]    ROMSTG STCK 9. 0x76ffe740 0x000000a8
[DEBUG]    ACPI GNVS  10. 0x76ffe700 0x00000038
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 4 / 0 ms
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
[DEBUG]  0x0000000077000000 - 0x000000007fffffff size 0x09000000 type 0
[DEBUG]  0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
[DEBUG]  0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
[DEBUG]  0x0000000100000000 - 0x00000001803fffff size 0x80400000 type 6
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 6/5.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
[DEBUG]  MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
[DEBUG]  MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
[DEBUG]  MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[INFO ]  LAPIC 0x2 in XAPIC mode.
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
[DEBUG]  MTRR: TEMPORARY Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
[DEBUG]  0x0000000077000000 - 0x00000000feffffff size 0x88000000 type 0
[DEBUG]  0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
[DEBUG]  0x0000000100000000 - 0x00000001803fffff size 0x80400000 type 6
[DEBUG]  MTRR: default type WB/UC MTRR counts: 10/5.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
[DEBUG]  MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
[DEBUG]  MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
[DEBUG]  MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[INFO ]  CBFS: Found 'fallback/payload' @0x11de80 size 0x13ee4b in mcache @0x76c2d350
[DEBUG]  Checking segment from ROM address 0xffd220ac
[DEBUG]  Checking segment from ROM address 0xffd220c8
[DEBUG]  Loading segment from ROM address 0xffd220ac
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xffd220e4 filesize 0x13ee13
[DEBUG]  Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x000000000013ee13
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xffd220c8
[DEBUG]    Entry Point 0x0080168c
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 708 / 0 ms
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
[INFO ]  HECI: Sending End-of-Post
[INFO ]  CSE: EOP requested action: continue boot
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 6 / 0 ms
[DEBUG]  mp_park_aps done after 0 msecs.
[DEBUG]  Jumping to boot code at 0x0080168c(0x76b59000)

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 bootblock starting (log level: 7)...
[DEBUG]  CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz
[DEBUG]  CPU: ID 906c0, Jasperlake A0, ucode: 24000024
[DEBUG]  CPU: AES supported, TXT NOT supported, VT supported
[DEBUG]  MCH: device id 4e22 (rev 00) is Jasperlake SKU4-1
[DEBUG]  PCH: device id 4d87 (rev 01) is Jasperlake Super
[DEBUG]  IGD: device id 4e55 (rev 01) is Jasperlake GT4
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0xc04000.
[DEBUG]  FMAP: base = 0xff000000 size = 0x1000000 #areas = 8
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: mcache @0xfef31a00 built for 19 files, used 0x3e0 of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x10b60 in mcache @0xfef31a2c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 1 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 romstage starting (log level: 7)...
[DEBUG]  pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00001c00
[DEBUG]  gpe0_sts[0]: 00000010 gpe0_en[0]: 00000000
[DEBUG]  gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
[DEBUG]  gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG]  gpe0_sts[3]: 00080040 gpe0_en[3]: 00000000
[DEBUG]  TCO_STS:   0000 0001
[DEBUG]  GEN_PMCON: d8a01a38 00002200
[DEBUG]  GBLRST_CAUSE: 00000040 00000000
[DEBUG]  prev_sleep_state 0
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'fspm.bin' @0x68dc0 size 0x79000 in mcache @0xfef31c98
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[DEBUG]  SPD INDEX = 0
[INFO ]  CBFS: Found 'spd.bin' @0x368c0 size 0x200 in mcache @0xfef31bd8
[INFO ]  SPD: module type is LPDDR4X
[INFO ]  SPD: module part number is                     
[INFO ]  SPD: banks 8, ranks 1, rows 16, columns 10, density 16384 Mb
[INFO ]  SPD: device width 16 bits, bus width 32 bits
[INFO ]  SPD: module size is 4096 MB (per channel)
[INFO ]  meminit_channels: DRAM half-populated
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x76fff000 254 entries.
[DEBUG]  IMD: root @ 0x76ffec00 62 entries.
[DEBUG]  FMAP: area RO_VPD found @ c00000 (16384 bytes)
[WARN ]  init_vpd_rdev: No RW_VPD FMAP section.
[DEBUG]  External stage cache:
[DEBUG]  IMD: root @ 0x7b3ff000 254 entries.
[DEBUG]  IMD: root @ 0x7b3fec00 62 entries.
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG]  MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG]  cse_lite: Number of partitions = 3
[DEBUG]  cse_lite: Current partition = RW
[DEBUG]  cse_lite: Next partition = RW
[DEBUG]  cse_lite: Flags = 0x7
[DEBUG]  cse_lite: RO version = 13.50.11.1304 (Status=0x0, Start=0x1000, End=0xebfff)
[DEBUG]  cse_lite: RW version = 13.50.11.1304 (Status=0x0, Start=0x140000, End=0x2c2fff)
[DEBUG]  1 DIMMs found
[DEBUG]  SMM Memory Map
[DEBUG]  SMRAM       : 0x7b000000 0x800000
[DEBUG]   Subregion 0: 0x7b000000 0x200000
[DEBUG]   Subregion 1: 0x7b200000 0x200000
[DEBUG]   Subregion 2: 0x7b400000 0x400000
[DEBUG]  top_of_ram = 0x77000000
[DEBUG]  Normal boot
[INFO ]  CBFS: Found 'fallback/postcar' @0x118740 size 0x56d4 in mcache @0xfef31d0c
[DEBUG]  Loading module at 0x76c1f000 with entry 0x76c1f031. filesize: 0x5348 memsize: 0xb698
[DEBUG]  Processing 211 relocs. Offset value of 0x74c1f000
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 2 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 postcar starting (log level: 7)...
[DEBUG]  Normal boot
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'fallback/ramstage' @0x15d40 size 0x1f5e8 in mcache @0x76c2d10c
[DEBUG]  Loading module at 0x76bc6000 with entry 0x76bc6000. filesize: 0x42ad0 memsize: 0x57ed0
[DEBUG]  Processing 4633 relocs. Offset value of 0x72bc6000
[DEBUG]  BS: postcar times (exec / console): total (unknown) / 0 ms

[NOTE ]  coreboot-4.22-123-g822782a10016-MrChromebox-4.22.2-5-g822782a1001 Tue Feb 13 17:47:11 UTC 2024 x86_32 ramstage starting (log level: 7)...
[DEBUG]  Normal boot
[INFO ]  FW_CONFIG value from CBI is 0x60000040000
[INFO ]  fw_config match found: AUDIO_AMP=UNPROVISIONED
[INFO ]  GENERIC: 0.0 disabled by fw_config
[DEBUG]  microcode: sig=0x906c0 pf=0x1 revision=0x24000024
[DEBUG]  FMAP: area COREBOOT found @ c04200 (4177408 bytes)
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0x10c80 size 0x5000 in mcache @0x76c2d0ac
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CBFS: Found 'fsps.bin' @0xe1e00 size 0x36906 in mcache @0x76c2d2d8
[DEBUG]  Detected 2 core, 2 thread CPU.
[DEBUG]  Setting up SMI for CPU
[DEBUG]  IED base = 0x7b400000
[DEBUG]  IED size = 0x00400000
[INFO ]  Will perform SMM setup.
[INFO ]  CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  CPU: APIC: 00 enabled
[DEBUG]  CPU: APIC: 01 enabled
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 16 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 1 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x2 in XAPIC mode.
[INFO ]  AP: slot 1 apic_id 2, MCU rev: 0x24000024
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x198 memsize: 0x198
[DEBUG]  Processing 9 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x76be45cd
[DEBUG]  Installing permanent SMM handler to 0x7b000000
[DEBUG]  HANDLER      [0x7b1fc000-0x7b1ff6e8]

[DEBUG]  CPU 0
[DEBUG]    ss0        [0x7b1fbc00-0x7b1fc000]
[DEBUG]    stub0      [0x7b1f4000-0x7b1f4198]

[DEBUG]  CPU 1
[DEBUG]    ss1        [0x7b1fb800-0x7b1fbc00]
[DEBUG]    stub1      [0x7b1f3c00-0x7b1f3d98]

[DEBUG]  stacks       [0x7b000000-0x7b001000]
[DEBUG]  Loading module at 0x7b1fc000 with entry 0x7b1fca26. filesize: 0x3638 memsize: 0x36e8
[DEBUG]  Processing 182 relocs. Offset value of 0x7b1fc000
[DEBUG]  Loading module at 0x7b1f4000 with entry 0x7b1f4000. filesize: 0x198 memsize: 0x198
[DEBUG]  Processing 9 relocs. Offset value of 0x7b1f4000
[DEBUG]  smm_module_setup_stub: stack_top = 0x7b001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x200000
[DEBUG]  SMM Module: placing smm entry code at 7b1f3c00,  cpu # 0x1
[DEBUG]  SMM Module: stub loaded at 7b1f4000. Will call 0x7b1fca26
[DEBUG]  Clearing SMI status registers
[DEBUG]  TCO_STS: INTRD_DET 
[DEBUG]  GPE0 STD STS: TCO_SCI 
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ec000, cpu = 0
[DEBUG]  In relocation handler: CPU 0
[DEBUG]  New SMBASE=0x7b1ec000 IEDBASE=0x7b400000
[DEBUG]  Writing SMRR. base = 0x7b000006, mask=0xff800c00
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ebc00, cpu = 1
[DEBUG]  In relocation handler: CPU 1
[DEBUG]  New SMBASE=0x7b1ebc00 IEDBASE=0x7b400000
[DEBUG]  Writing SMRR. base = 0x7b000006, mask=0xff800c00
[DEBUG]  Relocation complete.
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 906c0
[DEBUG]  CPU: family 06, model 9c, stepping 00
[DEBUG]  Clearing out pending MCEs
[INFO ]  Turbo is available but hidden
[INFO ]  Turbo is available and visible
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #1
[DEBUG]  CPU: vendor Intel device 906c0
[DEBUG]  CPU: family 06, model 9c, stepping 00
[DEBUG]  Clearing out pending MCEs
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  CPU #1 initialized
[INFO ]  bsp_do_flight_plan done after 1 msecs.
[DEBUG]  CPU: frequency set to 2800 MHz
[DEBUG]  Enabling SMIs.
[DEBUG]  BS: BS_DEV_INIT_CHIPS entry times (exec / console): 41 / 0 ms
[INFO ]  Probing TPM: . done!
[INFO ]  TPM ready after 0 ms
[INFO ]  Connected to device vid:did:rid of 1ae0:0028:00
[INFO ]  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_A:0.5.215/cr50_v2.94_mp.294-221da5d8be
[INFO ]  Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
[INFO ]  Initialized TPM device CR50 revision 0
[INFO ]  CBFS: Found 'vbt.bin' @0x68880 size 0x4b4 in mcache @0x76c2d268
[INFO ]  Found a VBT of 7680 bytes
[DEBUG]  WEAK: src/soc/intel/jasperlake/fsp_params.c/mainboard_silicon_init_params called
[DEBUG]  Detected 2 core, 2 thread CPU.
[DEBUG]  Detected 2 core, 2 thread CPU.
[INFO ]  FSPS returned 0
[DEBUG]  Display FSP Version Info HOB
[DEBUG]  Reference Code - CPU = 8.7.22.30
[DEBUG]  uCode Version = 24.0.0.24
[DEBUG]  TXT ACM version = ff.ff.ff.ffff
[DEBUG]  Reference Code - ME = 8.7.22.30
[DEBUG]  MEBx version = 0.0.0.0
[DEBUG]  ME Firmware Version = Lite SKU
[DEBUG]  Reference Code - PCH = 8.7.22.30
[DEBUG]  PCH-CRID Status = Disabled
[DEBUG]  PCH-CRID Original Value = ff.ff.ff.ffff
[DEBUG]  PCH-CRID New Value = ff.ff.ff.ffff
[DEBUG]  OPROM - RST - RAID = ff.ff.ff.ffff
[DEBUG]  PCH Hsio Version = 4.0.0.0
[DEBUG]  Reference Code - SA - System Agent = 8.7.22.30
[DEBUG]  Reference Code - MRC = 0.0.4.68
[DEBUG]  SA - PCIe Version = 8.7.22.30
[DEBUG]  SA-CRID Status = Disabled
[DEBUG]  SA-CRID Original Value = 0.0.0.0
[DEBUG]  SA-CRID New Value = 0.0.0.0
[DEBUG]  OPROM - VBIOS = ff.ff.ff.ffff
[DEBUG]  IO Manageability Engine FW Version = ff.ff.ff.ffff
[DEBUG]  PHY Build Version = ff.ff.ff.ffff
[DEBUG]  Thunderbolt(TM) FW Version = ff.ff.ff.ffff
[DEBUG]  System Agent Manageability Engine FW Version = ff.ff.ff.ffff
[DEBUG]  BS: BS_DEV_INIT_CHIPS run times (exec / console): 151 / 0 ms
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 0000 enabled
[DEBUG]  DOMAIN: 0000 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 00
[DEBUG]  PCI: 00:00.0 [8086/4e22] enabled
[DEBUG]  PCI: 00:02.0 [8086/4e55] enabled
[DEBUG]  PCI: 00:04.0 [8086/4e03] enabled
[DEBUG]  PCI: 00:08.0 [8086/4e11] enabled
[DEBUG]  PCI: 00:14.0 [8086/4ded] enabled
[DEBUG]  PCI: 00:14.2 [8086/4def] disabled
[DEBUG]  PCI: 00:14.3 [8086/4df0] enabled
[DEBUG]  PCI: 00:14.5 [8086/4df8] enabled
[DEBUG]  PCI: 00:15.0 [8086/4de8] enabled
[DEBUG]  PCI: 00:15.1 [8086/4de9] enabled
[DEBUG]  PCI: 00:15.2 [8086/4dea] enabled
[DEBUG]  PCI: 00:15.3 [8086/4deb] enabled
[DEBUG]  PCI: 00:16.0 [8086/4de0] enabled
[DEBUG]  PCI: 00:19.0 [8086/4dc5] enabled
[DEBUG]  PCI: 00:19.2 [8086/4dc7] enabled
[DEBUG]  PCI: 00:1a.0 [8086/4dc4] enabled
[DEBUG]  PCI: 00:1e.0 [8086/4da8] disabled
[DEBUG]  PCI: 00:1e.2 [8086/4daa] enabled
[DEBUG]  PCI: 00:1f.0 [8086/4d87] enabled
[INFO ]  PCI: Static device PCI: 00:1f.1 not found, disabling it.
[DEBUG]  RTC Init
[INFO ]  Set power on after power failure.
[DEBUG]  Disabling Deep S3
[DEBUG]  Disabling Deep S3
[DEBUG]  Disabling Deep S4
[DEBUG]  Disabling Deep S4
[DEBUG]  Disabling Deep S5
[DEBUG]  Disabling Deep S5
[DEBUG]  PCI: 00:1f.2 [0000/0000] hidden
[DEBUG]  PCI: 00:1f.3 [8086/4dc8] enabled
[DEBUG]  PCI: 00:1f.5 [8086/4da4] enabled
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:12.6
[WARN ]  PCI: 00:05.0
[WARN ]  PCI: 00:09.0
[WARN ]  PCI: 00:14.1
[WARN ]  PCI: 00:16.1
[WARN ]  PCI: 00:16.4
[WARN ]  PCI: 00:16.5
[WARN ]  PCI: 00:17.0
[WARN ]  PCI: 00:19.1
[WARN ]  PCI: 00:1e.1
[WARN ]  PCI: 00:1e.3
[WARN ]  PCI: 00:1f.1
[WARN ]  PCI: 00:1f.4
[WARN ]  PCI: 00:1f.7
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:02.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:02.0 finished in 0 msecs
[DEBUG]  PCI: 00:04.0 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  bus: PCI: 00:04.0[0]->scan_bus: bus PCI: 00:04.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.0 scanning...
[DEBUG]  USB0 port 0 enabled
[DEBUG]  USB0 port 0 scanning...
[DEBUG]  USB2 port 0 enabled
[DEBUG]  USB2 port 1 enabled
[DEBUG]  USB2 port 2 enabled
[DEBUG]  USB2 port 3 enabled
[DEBUG]  USB2 port 4 disabled
[DEBUG]  USB2 port 5 enabled
[DEBUG]  USB2 port 6 disabled
[DEBUG]  USB2 port 7 enabled
[DEBUG]  USB3 port 0 enabled
[DEBUG]  USB3 port 1 enabled
[DEBUG]  USB3 port 2 enabled
[DEBUG]  USB3 port 3 enabled
[DEBUG]  USB2 port 0 scanning...
[DEBUG]  scan_bus: bus USB2 port 0 finished in 0 msecs
[DEBUG]  USB2 port 1 scanning...
[DEBUG]  scan_bus: bus USB2 port 1 finished in 0 msecs
[DEBUG]  USB2 port 2 scanning...
[DEBUG]  scan_bus: bus USB2 port 2 finished in 0 msecs
[DEBUG]  USB2 port 3 scanning...
[DEBUG]  scan_bus: bus USB2 port 3 finished in 0 msecs
[DEBUG]  USB2 port 5 scanning...
[DEBUG]  scan_bus: bus USB2 port 5 finished in 0 msecs
[DEBUG]  USB2 port 7 scanning...
[DEBUG]  scan_bus: bus USB2 port 7 finished in 0 msecs
[DEBUG]  USB3 port 0 scanning...
[DEBUG]  scan_bus: bus USB3 port 0 finished in 0 msecs
[DEBUG]  USB3 port 1 scanning...
[DEBUG]  scan_bus: bus USB3 port 1 finished in 0 msecs
[DEBUG]  USB3 port 2 scanning...
[DEBUG]  scan_bus: bus USB3 port 2 finished in 0 msecs
[DEBUG]  USB3 port 3 scanning...
[DEBUG]  scan_bus: bus USB3 port 3 finished in 0 msecs
[DEBUG]  scan_bus: bus USB0 port 0 finished in 0 msecs
[DEBUG]  scan_bus: bus PCI: 00:14.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.3 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:14.3 finished in 0 msecs
[DEBUG]  PCI: 00:15.0 scanning...
[DEBUG]  I2C: 00:15 enabled
[DEBUG]  I2C: 00:40 enabled
[DEBUG]  scan_bus: bus PCI: 00:15.0 finished in 0 msecs
[DEBUG]  PCI: 00:15.1 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.1 finished in 0 msecs
[DEBUG]  PCI: 00:15.2 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.2 finished in 0 msecs
[DEBUG]  PCI: 00:15.3 scanning...
[DEBUG]  scan_bus: bus PCI: 00:15.3 finished in 0 msecs
[DEBUG]  PCI: 00:19.0 scanning...
[DEBUG]  I2C: 00:1a enabled
[DEBUG]  scan_bus: bus PCI: 00:19.0 finished in 0 msecs
[DEBUG]  PCI: 00:1e.2 scanning...
[DEBUG]  SPI: 00 enabled
[DEBUG]  bus: PCI: 00:1e.2[0]->scan_bus: bus PCI: 00:1e.2 finished in 0 msecs
[DEBUG]  PCI: 00:1f.0 scanning...
[DEBUG]  PNP: 0c09.0 enabled
[DEBUG]  PNP: 0c09.0 scanning...
[DEBUG]  scan_bus: bus PNP: 0c09.0 finished in 0 msecs
[DEBUG]  scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
[DEBUG]  PCI: 00:1f.3 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  GENERIC: 0.0 disabled
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
[DEBUG]  scan_bus: bus DOMAIN: 0000 finished in 1 msecs
[DEBUG]  scan_bus: bus Root Device finished in 1 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms
[INFO ]  MRC: Could not find region 'UNIFIED_MRC_CACHE'
[DEBUG]  FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
[INFO ]  MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
[DEBUG]  found VGA at PCI: 00:02.0
[DEBUG]  Setting up VGA for PCI: 00:02.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[DEBUG]  SA MMIO resource: PCIEXBAR ->  base = 0xc0000000, size = 0x10000000
[DEBUG]  SA MMIO resource: MCHBAR   ->  base = 0xfea80000, size = 0x00008000
[DEBUG]  SA MMIO resource: DMIBAR   ->  base = 0xfeda0000, size = 0x00001000
[DEBUG]  SA MMIO resource: EPBAR    ->  base = 0xfeda1000, size = 0x00001000
[DEBUG]  SA MMIO resource: REGBAR   ->  base = 0xfb000000, size = 0x00001000
[DEBUG]  SA MMIO resource: EDRAMBAR ->  base = 0xfed80000, size = 0x00004000
[DEBUG]  SA MMIO resource: GFXVTBAR ->  base = 0xfed90000, size = 0x00001000
[DEBUG]  SA MMIO resource: IPUVTBAR ->  base = 0xfed92000, size = 0x00001000
[DEBUG]  SA MMIO resource: VTVC0BAR ->  base = 0xfed91000, size = 0x00001000
[INFO ]  Available memory above 4GB: 2052M
[INFO ]  Done reading resources.
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 1 (relative placement) ===
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 84 base 00000800 limit 000008ff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 88 base 00000200 limit 0000020f io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 8c base 00000900 limit 000009ff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 90 base 00000080 limit 0000008f io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 1000, Size: 800, Tag: 100
[INFO ]   * Base: 1900, Size: e700, Tag: 100
[DEBUG]    PCI: 00:02.0 20 *  [0x1000 - 0x103f] limit: 103f io
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 0000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff
[DEBUG]  DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 01 base fea80000 limit fea87fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 08 base fed91000 limit fed91fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0a base 000c0000 limit 76ffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0b base 77000000 limit 7fbfffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0c base 100000000 limit 1803fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0d base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00.0 0e base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:19.2 10 base fe032000 limit fe032fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.0 98 base fe0b0000 limit fe0bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.2 10 base fe000000 limit fe00ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:1f.5 00 base ff000000 limit ffffffff mem (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 7fc00000, Size: 40400000, Tag: 200
[INFO ]   * Base: d0000000, Size: 10000000, Tag: 200
[INFO ]   * Base: 180400000, Size: 7e7fc00000, Tag: 200
[DEBUG]    PCI: 00:02.0 18 *  [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
[DEBUG]    PCI: 00:02.0 10 *  [0x90000000 - 0x90ffffff] limit: 90ffffff mem
[DEBUG]    PCI: 00:1f.3 20 *  [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
[DEBUG]    PCI: 00:04.0 10 *  [0x7fd00000 - 0x7fd0ffff] limit: 7fd0ffff mem
[DEBUG]    PCI: 00:14.0 10 *  [0x7fd10000 - 0x7fd1ffff] limit: 7fd1ffff mem
[DEBUG]    PCI: 00:14.3 10 *  [0x7fd20000 - 0x7fd23fff] limit: 7fd23fff mem
[DEBUG]    PCI: 00:1f.3 10 *  [0x7fd24000 - 0x7fd27fff] limit: 7fd27fff mem
[DEBUG]    PCI: 00:08.0 10 *  [0x7fd28000 - 0x7fd28fff] limit: 7fd28fff mem
[DEBUG]    PCI: 00:14.5 10 *  [0x7fd29000 - 0x7fd29fff] limit: 7fd29fff mem
[DEBUG]    PCI: 00:15.0 10 *  [0x7fd2a000 - 0x7fd2afff] limit: 7fd2afff mem
[DEBUG]    PCI: 00:15.1 10 *  [0x7fd2b000 - 0x7fd2bfff] limit: 7fd2bfff mem
[DEBUG]    PCI: 00:15.2 10 *  [0x7fd2c000 - 0x7fd2cfff] limit: 7fd2cfff mem
[DEBUG]    PCI: 00:15.3 10 *  [0x7fd2d000 - 0x7fd2dfff] limit: 7fd2dfff mem
[DEBUG]    PCI: 00:16.0 10 *  [0x7fd2e000 - 0x7fd2efff] limit: 7fd2efff mem
[DEBUG]    PCI: 00:19.0 10 *  [0x7fd2f000 - 0x7fd2ffff] limit: 7fd2ffff mem
[DEBUG]    PCI: 00:19.2 18 *  [0x7fd30000 - 0x7fd30fff] limit: 7fd30fff mem
[DEBUG]    PCI: 00:1a.0 10 *  [0x7fd31000 - 0x7fd31fff] limit: 7fd31fff mem
[DEBUG]    PCI: 00:1e.2 10 *  [0x7fd32000 - 0x7fd32fff] limit: 7fd32fff mem
[DEBUG]    PCI: 00:1f.5 10 *  [0x7fd33000 - 0x7fd33fff] limit: 7fd33fff mem
[DEBUG]  DOMAIN: 0000 mem: base: 77000000 size: 0 align: 0 gran: 0 limit: dfffffff done
[DEBUG]  DOMAIN: 0000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[DEBUG]  PCI: 00:02.0 10 <- [0x0000000090000000 - 0x0000000090ffffff] size 0x01000000 gran 0x18 mem64
[DEBUG]  PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG]  PCI: 00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
[DEBUG]  PCI: 00:04.0 10 <- [0x000000007fd00000 - 0x000000007fd0ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:08.0 10 <- [0x000000007fd28000 - 0x000000007fd28fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:14.0 10 <- [0x000000007fd10000 - 0x000000007fd1ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:14.3 10 <- [0x000000007fd20000 - 0x000000007fd23fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:14.5 10 <- [0x000000007fd29000 - 0x000000007fd29fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.0 10 <- [0x000000007fd2a000 - 0x000000007fd2afff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.1 10 <- [0x000000007fd2b000 - 0x000000007fd2bfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.2 10 <- [0x000000007fd2c000 - 0x000000007fd2cfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:15.3 10 <- [0x000000007fd2d000 - 0x000000007fd2dfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:16.0 10 <- [0x000000007fd2e000 - 0x000000007fd2efff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:19.0 10 <- [0x000000007fd2f000 - 0x000000007fd2ffff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:19.2 18 <- [0x000000007fd30000 - 0x000000007fd30fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1a.0 10 <- [0x000000007fd31000 - 0x000000007fd31fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1e.2 10 <- [0x000000007fd32000 - 0x000000007fd32fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1f.3 10 <- [0x000000007fd24000 - 0x000000007fd27fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:1f.3 20 <- [0x000000007fc00000 - 0x000000007fcfffff] size 0x00100000 gran 0x14 mem64
[DEBUG]  PCI: 00:1f.5 10 <- [0x000000007fd33000 - 0x000000007fd33fff] size 0x00001000 gran 0x0c mem
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 3 / 0 ms
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00.0 subsystem <- 8086/4e22
[DEBUG]  PCI: 00:00.0 cmd <- 06
[DEBUG]  PCI: 00:02.0 subsystem <- 8086/4e55
[DEBUG]  PCI: 00:02.0 cmd <- 03
[DEBUG]  PCI: 00:04.0 subsystem <- 8086/4e03
[DEBUG]  PCI: 00:04.0 cmd <- 02
[DEBUG]  PCI: 00:08.0 subsystem <- 8086/4e11
[DEBUG]  PCI: 00:08.0 cmd <- 06
[DEBUG]  PCI: 00:14.0 subsystem <- 8086/4ded
[DEBUG]  PCI: 00:14.0 cmd <- 02
[DEBUG]  PCI: 00:14.3 subsystem <- 8086/4df0
[DEBUG]  PCI: 00:14.3 cmd <- 02
[DEBUG]  PCI: 00:14.5 subsystem <- 8086/4df8
[DEBUG]  PCI: 00:14.5 cmd <- 06
[DEBUG]  PCI: 00:15.0 subsystem <- 8086/4de8
[DEBUG]  PCI: 00:15.0 cmd <- 02
[DEBUG]  PCI: 00:15.1 subsystem <- 8086/4de9
[DEBUG]  PCI: 00:15.1 cmd <- 02
[DEBUG]  PCI: 00:15.2 subsystem <- 8086/4dea
[DEBUG]  PCI: 00:15.2 cmd <- 02
[DEBUG]  PCI: 00:15.3 subsystem <- 8086/4deb
[DEBUG]  PCI: 00:15.3 cmd <- 02
[DEBUG]  PCI: 00:16.0 subsystem <- 8086/4de0
[DEBUG]  PCI: 00:16.0 cmd <- 02
[DEBUG]  PCI: 00:19.0 subsystem <- 8086/4dc5
[DEBUG]  PCI: 00:19.0 cmd <- 02
[DEBUG]  PCI: 00:19.2 subsystem <- 8086/4dc7
[DEBUG]  PCI: 00:19.2 cmd <- 06
[DEBUG]  PCI: 00:1a.0 subsystem <- 8086/4dc4
[DEBUG]  PCI: 00:1a.0 cmd <- 06
[DEBUG]  PCI: 00:1e.2 subsystem <- 8086/4daa
[DEBUG]  PCI: 00:1e.2 cmd <- 06
[DEBUG]  PCI: 00:1f.0 subsystem <- 8086/4d87
[DEBUG]  PCI: 00:1f.0 cmd <- 407
[DEBUG]  PCI: 00:1f.3 subsystem <- 8086/4dc8
[DEBUG]  PCI: 00:1f.3 cmd <- 02
[DEBUG]  PCI: 00:1f.5 subsystem <- 8086/4da4
[DEBUG]  PCI: 00:1f.5 cmd <- 406
[INFO ]  done.
[INFO ]  Initializing devices...
[DEBUG]  Root Device init
[INFO ]  mainboard: EC init
[DEBUG]  Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG]  Chrome EC: UHEPI supported
[DEBUG]  Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
[DEBUG]  Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
[DEBUG]  Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001009105e
[DEBUG]  Chrome EC: Set WAKE mask to 0x0000000000000000
[DEBUG]  Root Device init finished in 1 msecs
[DEBUG]  PCI: 00:00.0 init
[INFO ]  CPU TDP = 6 Watts
[INFO ]  CPU PL1 = 6 Watts
[INFO ]  CPU PL2 = 20 Watts
[DEBUG]  PCI: 00:00.0 init finished in 1 msecs
[DEBUG]  PCI: 00:02.0 init
[INFO ]  GMA: Found VBT in CBFS
[INFO ]  GMA: Found valid VBT in CBFS
[INFO ]  framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32
[INFO ]                     x_res x y_res: 1366 x 768, size: 4227072 at 0x80000000
[DEBUG]  PCI: 00:02.0 init finished in 0 msecs
[DEBUG]  PCI: 00:08.0 init
[DEBUG]  PCI: 00:08.0 init finished in 0 msecs
[DEBUG]  PCI: 00:14.0 init
[DEBUG]  XHCI: Updated LFPS sampling OFF time to 9 ms
[DEBUG]  PCI: 00:14.0 init finished in 0 msecs
[DEBUG]  PCI: 00:15.0 init
[DEBUG]  I2C bus 0 version 0x3230302a
[INFO ]  DW I2C bus 0 at 0x7fd2a000 (400 KHz)
[DEBUG]  PCI: 00:15.0 init finished in 0 msecs
[DEBUG]  PCI: 00:15.1 init
[DEBUG]  I2C bus 1 version 0x3230302a
[INFO ]  DW I2C bus 1 at 0x7fd2b000 (400 KHz)
[DEBUG]  PCI: 00:15.1 init finished in 0 msecs
[DEBUG]  PCI: 00:15.2 init
[DEBUG]  I2C bus 2 version 0x3230302a
[INFO ]  DW I2C bus 2 at 0x7fd2c000 (400 KHz)
[DEBUG]  PCI: 00:15.2 init finished in 0 msecs
[DEBUG]  PCI: 00:15.3 init
[DEBUG]  I2C bus 3 version 0x3230302a
[INFO ]  DW I2C bus 3 at 0x7fd2d000 (400 KHz)
[DEBUG]  PCI: 00:15.3 init finished in 0 msecs
[DEBUG]  PCI: 00:16.0 init
[DEBUG]  PCI: 00:16.0 init finished in 0 msecs
[DEBUG]  PCI: 00:19.0 init
[DEBUG]  I2C bus 4 version 0x3230302a
[INFO ]  DW I2C bus 4 at 0x7fd2f000 (400 KHz)
[DEBUG]  PCI: 00:19.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1a.0 init
[DEBUG]  PCI: 00:1a.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1f.0 init
[DEBUG]  IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: ID = 0x00
[DEBUG]  IOAPIC: 120 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[DEBUG]  PCI: 00:1f.0 init finished in 0 msecs
[DEBUG]  PCI: 00:1f.2 init
[DEBUG]  apm_control: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  PCI: 00:1f.2 init finished in 1 msecs
[DEBUG]  PCI: 00:1f.3 init
[DEBUG]  PCI: 00:1f.3 init finished in 0 msecs
[DEBUG]  PNP: 0c09.0 init
[DEBUG]  Google Chrome EC: Initializing
[DEBUG]  Google Chrome EC uptime: 1248.605 seconds
[DEBUG]  Google Chrome AP resets since EC boot: 1
[DEBUG]  Google Chrome most recent AP reset causes:
[DEBUG]     0.395: 32775 shutdown: entering G3
[DEBUG]  Google Chrome EC reset flags at last EC boot: reset-pin | power-on | sysjump
[DEBUG]  Google Chrome EC: version:
[DEBUG]     ro: sasukette_v2.0.10540-df222fb19
[DEBUG]     rw: sasukette_v2.0.22514-05e2f7f803
[DEBUG]    running image: 2
[INFO ]  CBFS: Found 'ecrw.hash' @0x68800 size 0x20 in mcache @0x76c2d244
[DEBUG]  ChromeEC SW Sync: Expected hash: 01f3b2044c741b45d57c535f5c68daf0c59cb910ffd1d76a27516c706880a0ec
[DEBUG]  ChromeEC: Getting hash:
[DEBUG]  ChromeEC: No valid hash (status=0 size=0). Compute one...
[DEBUG]  ChromeEC: Starting EC hash:
[DEBUG]  ChromeEC SW Sync: current EC_RW hash: b14cca7d78a45093c344d2ae3d6e5738ae57d21a595b435dbf55586854339b51
[DEBUG]  ChromeEC SW Sync: updating EC_RW...
[INFO ]  CBFS: Found 'ecrw' @0x39f80 size 0x2e85c in mcache @0x76c2d224
[DEBUG]  Getting EC region info
[ERROR]  ChromeEC SW Sync: Failed to update EC_RW.
[ERROR]  ChromeEC: EC SW SYNC FAILED
[DEBUG]  PNP: 0c09.0 init finished in 649 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 655 / 0 ms
[DEBUG]  FMAP: area SMMSTORE found @ bc0000 (262144 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
[DEBUG]  smm store: 4 # blocks with size 0x10000
[INFO ]  SMMSTORE: Setting up SMI handler
[INFO ]  tlcl_send_startup: Startup return code is 0x0
[INFO ]  TPM: setup succeeded
[DEBUG]  BS: BS_DEV_INIT exit times (exec / console): 50 / 0 ms
[INFO ]  Finalize devices...
[DEBUG]  PCI: 00:02.0 final
[DEBUG]  PCI: 00:16.0 final
[DEBUG]  CSE RW Firmware Version: 0.0.0.0
[DEBUG]  PCI: 00:1f.2 final
[INFO ]  Devices finalized
[DEBUG]  ME: HFSTS1                      : 0x90000245
[DEBUG]  ME: HFSTS2                      : 0x86100126
[DEBUG]  ME: HFSTS3                      : 0x00000050
[DEBUG]  ME: HFSTS4                      : 0x00004000
[DEBUG]  ME: HFSTS5                      : 0x00000000
[DEBUG]  ME: HFSTS6                      : 0x40400006
[DEBUG]  ME: Manufacturing Mode          : NO
[DEBUG]  ME: SPI Protection Mode Enabled : YES
[DEBUG]  ME: FW Partition Table          : OK
[DEBUG]  ME: Bringup Loader Failure      : NO
[DEBUG]  ME: Firmware Init Complete      : YES
[DEBUG]  ME: Boot Options Present        : NO
[DEBUG]  ME: Update In Progress          : NO
[DEBUG]  ME: D0i3 Support                : YES
[DEBUG]  ME: Low Power State Enabled     : NO
[DEBUG]  ME: CPU Replaced                : NO
[DEBUG]  ME: CPU Replacement Valid       : YES
[DEBUG]  ME: Current Working State       : 5
[DEBUG]  ME: Current Operation State     : 1
[DEBUG]  ME: Current Operation Mode      : 0
[DEBUG]  ME: Error Code                  : 0
[DEBUG]  ME: CPU Debug Disabled          : YES
[DEBUG]  ME: TXT Support                 : NO
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x36b00 size 0x3420 in mcache @0x76c2d1f8
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 76b35000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  SCI is IRQ 9, GSI 9
[DEBUG]  ACPI:    * FACP
[DEBUG]  ACPI: added table 1/32, length now 44
[DEBUG]  Found 1 CPU(s) with 2/2 physical/logical core(s) each.
[DEBUG]  PCI space above 4GB MMIO is at 0x180400000, len = 0x7e7fc00000
[DEBUG]  Empty min sleep state array returned
[INFO ]  Returning default LPI constraint package
[INFO ]  \_SB.PCI0.PEPD: Intel Power Engine Plug-in
[INFO ]  \_SB.DPTF: Intel DPTF at GENERIC: 0.0
[INFO ]  \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ]  \_SB.PCI0.I2C4.DLG7: Dialog Semiconductor DA7219 Audio Codec address 01ah irq 0
[INFO ]  \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
[INFO ]  PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
[INFO ]  PS2K: Passing 80 keymaps to kernel
[INFO ]  PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ]
[INFO ]  \_SB.PCI0.HDAS.MAXM: Maxim Integrated 98357A Amplifier
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port at USB2 port 1
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS03: Left Type-A Port at USB2 port 2
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS04: Right Type-A Port at USB2 port 3
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS06: UFCamera at USB2 port 5
[INFO ]  \_SB.PCI0.XHCI.RHUB.HS08: Bluetooth at USB2 port 7
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port at USB3 port 1
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
[INFO ]  \_SB.PCI0.XHCI.RHUB.SS04: LTE at USB3 port 3
[DEBUG]  ACPI:    * SSDT
[DEBUG]  ACPI: added table 2/32, length now 52
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 60
[DEBUG]  TPM2 log created at 0x76b25000
[DEBUG]  ACPI:    * TPM2
[DEBUG]  ACPI: added table 4/32, length now 68
[DEBUG]  ACPI:    * LPIT
[DEBUG]  ACPI: added table 5/32, length now 76
[DEBUG]  IOAPIC: 120 interrupts
[DEBUG]  SCI is IRQ 9, GSI 9
[DEBUG]  ACPI:    * APIC
[DEBUG]  ACPI: added table 6/32, length now 84
[DEBUG]  current = 76b3a950
[DEBUG]  ACPI:    * DMAR
[DEBUG]  ACPI: added table 7/32, length now 92
[DEBUG]  ACPI: added table 8/32, length now 100
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 9/32, length now 108
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 23184 bytes.
[DEBUG]  smbios_write_tables: 76b1d000
[DEBUG]  BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-4.22.2-5-g822782a1001'
[INFO ]  Couldn't obtain OEM name from CBI
[INFO ]  Create SMBIOS type 16
[INFO ]  Create SMBIOS type 17
[INFO ]  Create SMBIOS type 20
[INFO ]  GENERIC: 0.0 (WIFI Device)
[DEBUG]  SMBIOS tables: 867 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum f928
[DEBUG]  Writing coreboot table at 0x76b59000
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG]   3. 0000000000100000-0000000076b1cfff: RAM
[DEBUG]   4. 0000000076b1d000-0000000076bc5fff: CONFIGURATION TABLES
[DEBUG]   5. 0000000076bc6000-0000000076c1dfff: RAMSTAGE
[DEBUG]   6. 0000000076c1e000-0000000076ffffff: CONFIGURATION TABLES
[DEBUG]   7. 0000000077000000-000000007fbfffff: RESERVED
[DEBUG]   8. 00000000c0000000-00000000cfffffff: RESERVED
[DEBUG]   9. 00000000fb000000-00000000fb000fff: RESERVED
[DEBUG]  10. 00000000fe000000-00000000fe00ffff: RESERVED
[DEBUG]  11. 00000000fe0b0000-00000000fe0bffff: RESERVED
[DEBUG]  12. 00000000fea80000-00000000fea87fff: RESERVED
[DEBUG]  13. 00000000fed80000-00000000fed83fff: RESERVED
[DEBUG]  14. 00000000fed90000-00000000fed92fff: RESERVED
[DEBUG]  15. 00000000feda0000-00000000feda1fff: RESERVED
[DEBUG]  16. 00000000ff000000-00000000ffffffff: RESERVED
[DEBUG]  17. 0000000100000000-00000001803fffff: RAM
[INFO ]  Board ID: 5
[INFO ]  FW config: 0x60000040000
[DEBUG]  Wrote coreboot table at: 0x76b59000, 0x584 bytes, checksum c7a7
[DEBUG]  coreboot table: 1436 bytes.
[DEBUG]  IMD ROOT    0. 0x76fff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x76ffe000 0x00001000
[DEBUG]  FSP MEMORY  2. 0x76c4e000 0x003b0000
[DEBUG]  CONSOLE     3. 0x76c2e000 0x00020000
[DEBUG]  RO MCACHE   4. 0x76c2d000 0x000003e0
[DEBUG]  TIME STAMP  5. 0x76c2c000 0x00000910
[DEBUG]  MEM INFO    6. 0x76c2b000 0x00000f48
[DEBUG]  AFTER CAR   7. 0x76c1e000 0x0000d000
[DEBUG]  RAMSTAGE    8. 0x76bc5000 0x00059000
[DEBUG]  REFCODE     9. 0x76b85000 0x00040000
[DEBUG]  SMM BACKUP 10. 0x76b75000 0x00010000
[DEBUG]  IGD OPREGION11. 0x76b71000 0x00003c43
[DEBUG]  SMM COMBUFFER12. 0x76b61000 0x00010000
[DEBUG]  COREBOOT   13. 0x76b59000 0x00008000
[DEBUG]  ACPI       14. 0x76b35000 0x00024000
[DEBUG]  TPM2 TCGLOG15. 0x76b25000 0x00010000
[DEBUG]  SMBIOS     16. 0x76b1d000 0x00008000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x76ffec00 0x00000400
[DEBUG]    FSP RUNTIME 1. 0x76ffebe0 0x00000004
[DEBUG]    VPD         2. 0x76ffeac0 0x00000110
[DEBUG]    FMAP        3. 0x76ffe920 0x00000188
[DEBUG]    CSE BP INFO 4. 0x76ffe8a0 0x00000068
[DEBUG]    CSE SPECIFIC INFO 5. 0x76ffe880 0x00000020
[DEBUG]    POWER STATE 6. 0x76ffe840 0x00000040
[DEBUG]    FSPM VERSION 7. 0x76ffe820 0x00000004
[DEBUG]    ROMSTAGE    8. 0x76ffe800 0x00000004
[DEBUG]    ROMSTG STCK 9. 0x76ffe740 0x000000a8
[DEBUG]    ACPI GNVS  10. 0x76ffe700 0x00000038
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 4 / 0 ms
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
[DEBUG]  0x0000000077000000 - 0x000000007fffffff size 0x09000000 type 0
[DEBUG]  0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
[DEBUG]  0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
[DEBUG]  0x0000000100000000 - 0x00000001803fffff size 0x80400000 type 6
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 6/5.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
[DEBUG]  MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
[DEBUG]  MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
[DEBUG]  MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[INFO ]  LAPIC 0x2 in XAPIC mode.
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
[DEBUG]  MTRR: TEMPORARY Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x0000000076ffffff size 0x76f40000 type 6
[DEBUG]  0x0000000077000000 - 0x00000000feffffff size 0x88000000 type 0
[DEBUG]  0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
[DEBUG]  0x0000000100000000 - 0x00000001803fffff size 0x80400000 type 6
[DEBUG]  MTRR: default type WB/UC MTRR counts: 10/5.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
[DEBUG]  MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
[DEBUG]  MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
[DEBUG]  MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[INFO ]  CBFS: Found 'fallback/payload' @0x11de80 size 0x13ee4b in mcache @0x76c2d350
[DEBUG]  Checking segment from ROM address 0xffd220ac
[DEBUG]  Checking segment from ROM address 0xffd220c8
[DEBUG]  Loading segment from ROM address 0xffd220ac
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xffd220e4 filesize 0x13ee13
[DEBUG]  Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x000000000013ee13
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xffd220c8
[DEBUG]    Entry Point 0x0080168c
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 710 / 0 ms
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
[INFO ]  HECI: Sending End-of-Post
[INFO ]  CSE: EOP requested action: continue boot
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 7 / 0 ms
[DEBUG]  mp_park_aps done after 0 msecs.
[DEBUG]  Jumping to boot code at 0x0080168c(0x76b59000)

[MrChromebox]

this is a SASUKE board? cbmem shows no touchpad detected. Also EC update failing, which isn't good.

[kamahell87]

The board is SASUKETTE. The touchpad was definitely working with ChromeOS

[MrChromebox]

looks like SASUKETTE was not properly supported, but instead using the SASUKE image. I've gone ahead and added support for SASUKETTE, but in order to get the correct image, you will need to go back to ChromeOS first so the device is detected properly via the script. Please LMK if it's not detected properly

[kamahell87]

So, let me see if I got it right. I need to use use the stock firmware I backed up using your script, then install ChromeOS back, and finally do the whole procedure back again to install the Coreboot and then Linux.

[MrChromebox]

correct. There's no good way to force your device to go from sasuke to sasukette without manually flashing, and I don't want to do that over github

[kamahell87]

Perfect. I'll try to do the whole procedure before the end of the week. I'll keep you posted!

[kamahell87]

I went though the whole process and the touchpad is recognised as is should! The built in camera is working as well. The only issue, is the audio that doesn't come out but is being recognised in the settings. Thank you very much for your help and for your work!

[MrChromebox]

audio isn't going to work OOTB, will need to use the chrultrabook script for that. But that's an OS issue not a firmware one. Glad the others are working now though :)