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USB 3.0 add-on cards have issues with UAS/UASP under Samsung Chromebox Stumpy #652

Closed ShapeShifter499 closed 1 month ago

ShapeShifter499 commented 3 months ago

I'm running a Samsung Chromebox Stumpy and I tried adding a USB 3.0 card to the unused Mini PCIe slot but anything connected with UAS/UASP (USB Attached SCSI Protocol) tends to throw errors. I am at my wits end trying to figure out where the issue is. Enclosures that have UASP work fine when connected to a Surface Pro 5 I have running Linux.

I'm wondering if possibly the Coreboot build is missing some UASP specific settings.

So far I've tried UPD720202 Renesas based Mini PCIe card connected to a Mini PCIe flat ribbon extender. Fresco Logic FL1100 based PCIe card connected to a PCIe 1x to Mini PCIe adapter, which is then connected to the Mini PCIe flat ribbon extender.

In both cases I see these sort of messages. Enclosure here is a Nexstar HX.

[  243.863681] sd 7:0:0:0: [sdc] tag#26 uas_eh_abort_handler 0 uas-tag 23 inflight: CMD IN 
[  243.863690] sd 7:0:0:0: [sdc] tag#26 CDB: Read(16) 88 00 00 00 00 01 4e c0 98 d0 00 00 01 58 00 00
[  243.863852] sd 7:0:0:0: [sdc] tag#25 uas_eh_abort_handler 0 uas-tag 22 inflight: CMD IN 
[  243.863854] sd 7:0:0:0: [sdc] tag#25 CDB: Read(16) 88 00 00 00 00 01 4e c0 98 30 00 00 00 70 00 00
[  243.863986] sd 7:0:0:0: [sdc] tag#24 uas_eh_abort_handler 0 uas-tag 21 inflight: CMD IN 
[  243.863988] sd 7:0:0:0: [sdc] tag#24 CDB: Read(16) 88 00 00 00 00 01 4e c0 98 08 00 00 00 08 00 00
[  243.864115] sd 7:0:0:0: [sdc] tag#23 uas_eh_abort_handler 0 uas-tag 20 inflight: CMD IN 
[  243.864117] sd 7:0:0:0: [sdc] tag#23 CDB: Read(16) 88 00 00 00 00 01 4e c0 97 e8 00 00 00 08 00 00
[  243.864238] sd 7:0:0:0: [sdc] tag#22 uas_eh_abort_handler 0 uas-tag 19 inflight: CMD IN 
[  243.864240] sd 7:0:0:0: [sdc] tag#22 CDB: Read(16) 88 00 00 00 00 01 4e c0 97 90 00 00 00 50 00 00
[  243.864343] sd 7:0:0:0: [sdc] tag#21 uas_eh_abort_handler 0 uas-tag 18 inflight: CMD IN 
[  243.864345] sd 7:0:0:0: [sdc] tag#21 CDB: Read(16) 88 00 00 00 00 01 4e c0 97 78 00 00 00 08 00 00
[  243.864472] sd 7:0:0:0: [sdc] tag#20 uas_eh_abort_handler 0 uas-tag 17 inflight: CMD IN 
[  243.864474] sd 7:0:0:0: [sdc] tag#20 CDB: Read(16) 88 00 00 00 00 01 4e c0 97 38 00 00 00 38 00 00
[  243.864613] sd 7:0:0:0: [sdc] tag#19 uas_eh_abort_handler 0 uas-tag 16 inflight: CMD IN 
[  243.864626] sd 7:0:0:0: [sdc] tag#19 CDB: Read(16) 88 00 00 00 00 01 4e c0 90 00 00 00 03 50 00 00
[  243.864763] sd 7:0:0:0: [sdc] tag#18 uas_eh_abort_handler 0 uas-tag 15 inflight: CMD IN 
[  243.864770] sd 7:0:0:0: [sdc] tag#18 CDB: Read(16) 88 00 00 00 00 01 4e c0 8f c0 00 00 00 38 00 00
[  243.864914] sd 7:0:0:0: [sdc] tag#17 uas_eh_abort_handler 0 uas-tag 14 inflight: CMD IN 
[  243.864921] sd 7:0:0:0: [sdc] tag#17 CDB: Read(16) 88 00 00 00 00 01 4e c0 8d 18 00 00 02 90 00 00
[  243.865066] sd 7:0:0:0: [sdc] tag#16 uas_eh_abort_handler 0 uas-tag 13 inflight: CMD IN 
[  243.865067] sd 7:0:0:0: [sdc] tag#16 CDB: Read(16) 88 00 00 00 00 01 4e c0 8d 00 00 00 00 08 00 00
[  243.865196] sd 7:0:0:0: [sdc] tag#15 uas_eh_abort_handler 0 uas-tag 10 inflight: CMD IN 
[  243.865202] sd 7:0:0:0: [sdc] tag#15 CDB: Read(16) 88 00 00 00 00 01 4e c0 89 b8 00 00 00 08 00 00
[  243.865297] sd 7:0:0:0: [sdc] tag#14 uas_eh_abort_handler 0 uas-tag 9 inflight: CMD 
[  243.865308] sd 7:0:0:0: [sdc] tag#14 CDB: Read(16) 88 00 00 00 00 01 4e c0 89 10 00 00 00 a0 00 00
[  243.865310] sd 7:0:0:0: [sdc] tag#13 uas_eh_abort_handler 0 uas-tag 12 inflight: CMD IN 
[  243.865311] sd 7:0:0:0: [sdc] tag#13 CDB: Read(16) 88 00 00 00 00 01 4e c0 8c f0 00 00 00 08 00 00
[  243.865439] sd 7:0:0:0: [sdc] tag#12 uas_eh_abort_handler 0 uas-tag 11 inflight: CMD IN 
[  243.865445] sd 7:0:0:0: [sdc] tag#12 CDB: Read(16) 88 00 00 00 00 01 4e c0 89 d0 00 00 02 80 00 00
[  243.865585] sd 7:0:0:0: [sdc] tag#10 uas_eh_abort_handler 0 uas-tag 8 inflight: CMD 
[  243.865592] sd 7:0:0:0: [sdc] tag#10 CDB: Read(16) 88 00 00 00 00 01 4e 80 a2 80 00 00 00 08 00 00
[  243.865599] sd 7:0:0:0: [sdc] tag#9 uas_eh_abort_handler 0 uas-tag 7 inflight: CMD 
[  243.865605] sd 7:0:0:0: [sdc] tag#9 CDB: Read(16) 88 00 00 00 00 01 4e 80 a2 50 00 00 00 08 00 00
[  243.865620] sd 7:0:0:0: [sdc] tag#8 uas_eh_abort_handler 0 uas-tag 6 inflight: CMD 
[  243.865622] sd 7:0:0:0: [sdc] tag#8 CDB: Read(16) 88 00 00 00 00 01 4e 80 a2 28 00 00 00 08 00 00
[  243.865624] sd 7:0:0:0: [sdc] tag#7 uas_eh_abort_handler 0 uas-tag 1 inflight: CMD IN 
[  243.865625] sd 7:0:0:0: [sdc] tag#7 CDB: Read(16) 88 00 00 00 00 01 4e 80 9f 50 00 00 00 70 00 00
[  243.880369] scsi host7: uas_eh_device_reset_handler start
[  244.003992] usb 4-2: reset SuperSpeed USB device number 3 using xhci_hcd
[  244.022473] scsi host7: uas_eh_device_reset_handler success

Stumpy running MrChromebox-4.22.4 Coreboot build.
Arch Linux 16GB RAM 512GB SSD

MrChromebox commented 3 months ago

cbmem log please

ShapeShifter499 commented 3 months ago

Coreboot updated to MrChromebox-2405.0

cbmem log with the FL1100 card inserted.

[kumo-chromebox ~]# cbmem -1
*** Pre-CBMEM romstage console overflowed, log truncated! ***
tatic northbridge registers... done
[DEBUG]  Initializing Graphics...
[DEBUG]  Back from systemagent_early_init()
[INFO ]  Intel ME early init
[INFO ]  Intel ME firmware is ready
[DEBUG]  ME: Requested 8MB UMA
[DEBUG]  Starting native Platform init
[DEBUG]  DMI: Running at X4 @ 5000MT/s
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 500000 (65536 bytes)
[DEBUG]  Trying stored timings.
[DEBUG]  Starting Sandy Bridge RAM training (fast boot).
[DEBUG]  100MHz reference clock support: no
[DEBUG]  PLL_REF100_CFG value: 0x0
[DEBUG]  Trying CAS 9, tCK 384.
[DEBUG]  Found compatible clock, CAS pair.
[DEBUG]  Selected DRAM frequency: 666 MHz
[DEBUG]  Selected CAS latency   : 9T
[DEBUG]  MPLL busy... done in 40 us
[DEBUG]  MPLL frequency is set at : 666 MHz
[DEBUG]  Done dimm mapping
[DEBUG]  Update PCI-E configuration space:
[DEBUG]  PCI(0, 0, 0)[a0] = 0
[DEBUG]  PCI(0, 0, 0)[a4] = 2
[DEBUG]  PCI(0, 0, 0)[bc] = 86a00000
[DEBUG]  PCI(0, 0, 0)[a8] = 78e00000
[DEBUG]  PCI(0, 0, 0)[ac] = 2
[DEBUG]  PCI(0, 0, 0)[b8] = 80000000
[DEBUG]  PCI(0, 0, 0)[b0] = 80a00000
[DEBUG]  PCI(0, 0, 0)[b4] = 80800000
[DEBUG]  PCI(0, 0, 0)[7c] = 7f
[DEBUG]  PCI(0, 0, 0)[70] = ff800000
[DEBUG]  PCI(0, 0, 0)[74] = 1
[DEBUG]  PCI(0, 0, 0)[78] = ff800c00
[DEBUG]  Done memory map
[DEBUG]  Done io registers
[DEBUG]  t123: 1768, 9120, 500
[NOTE ]  ME: FWS2: 0x164e0006
[NOTE ]  ME:  Bist in progress: 0x0
[NOTE ]  ME:  ICC Status      : 0x3
[NOTE ]  ME:  Invoke MEBx     : 0x0
[NOTE ]  ME:  CPU replaced    : 0x0
[NOTE ]  ME:  MBP ready       : 0x0
[NOTE ]  ME:  MFS failure     : 0x0
[NOTE ]  ME:  Warm reset req  : 0x0
[NOTE ]  ME:  CPU repl valid  : 0x0
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  FW update req   : 0x0
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  Current state   : 0x4e
[NOTE ]  ME:  Current PM event: 0x6
[NOTE ]  ME:  Progress code   : 0x1
[NOTE ]  Waited long enough, or CPU was not replaced, continue...
[NOTE ]  PASSED! Tell ME that DRAM is ready
[NOTE ]  ME: FWS2: 0x16500006
[NOTE ]  ME:  Bist in progress: 0x0
[NOTE ]  ME:  ICC Status      : 0x3
[NOTE ]  ME:  Invoke MEBx     : 0x0
[NOTE ]  ME:  CPU replaced    : 0x0
[NOTE ]  ME:  MBP ready       : 0x0
[NOTE ]  ME:  MFS failure     : 0x0
[NOTE ]  ME:  Warm reset req  : 0x0
[NOTE ]  ME:  CPU repl valid  : 0x0
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  FW update req   : 0x0
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  Current state   : 0x50
[NOTE ]  ME:  Current PM event: 0x6
[NOTE ]  ME:  Progress code   : 0x1
[NOTE ]  ME: Requested BIOS Action: Continue to boot
[DEBUG]  ME: FW Partition Table      : OK
[DEBUG]  ME: Bringup Loader Failure  : NO
[DEBUG]  ME: Firmware Init Complete  : NO
[DEBUG]  ME: Manufacturing Mode      : NO
[DEBUG]  ME: Boot Options Present    : NO
[DEBUG]  ME: Update In Progress      : NO
[DEBUG]  ME: Current Working State   : Normal
[DEBUG]  ME: Current Operation State : Bring up
[DEBUG]  ME: Current Operation Mode  : Normal
[DEBUG]  ME: Error Code              : No Error
[DEBUG]  ME: Progress Phase          : BUP Phase
[DEBUG]  ME: Power Management Event  : Pseudo-global reset
[DEBUG]  ME: Progress Phase State    : 0x50
[DEBUG]  memcfg DDR3 ref clock 133 MHz
[DEBUG]  memcfg DDR3 clock 1330 MHz
[DEBUG]  memcfg channel assignment: A: 0, B  1, C  2
[DEBUG]  memcfg channel[0] config (00620020):
[DEBUG]     ECC inactive
[DEBUG]     enhanced interleave mode on
[DEBUG]     rank interleave on
[DEBUG]     DIMMA 8192 MB width x8 dual rank, selected
[DEBUG]     DIMMB 0 MB width x8 single rank
[DEBUG]  memcfg channel[1] config (00000000):
[DEBUG]     ECC inactive
[DEBUG]     enhanced interleave mode off
[DEBUG]     rank interleave off
[DEBUG]     DIMMA 0 MB width x8 single rank, selected
[DEBUG]     DIMMB 0 MB width x8 single rank
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x7ffff000 254 entries.
[DEBUG]  IMD: root @ 0x7fffec00 62 entries.
[DEBUG]  FMAP: area RO_VPD found @ 550000 (16384 bytes)
[WARN ]  RO_VPD is uninitialized or empty.
[WARN ]  init_vpd_rdev: No RW_VPD FMAP section.
[DEBUG]  FMAP: area COREBOOT found @ 554200 (2801152 bytes)
[DEBUG]  External stage cache:
[DEBUG]  IMD: root @ 0x803ff000 254 entries.
[DEBUG]  IMD: root @ 0x803fec00 62 entries.
[DEBUG]  CBMEM entry for DIMM info: 0x7ffdc000
[DEBUG]  SMM Memory Map
[DEBUG]  SMRAM       : 0x80000000 0x800000
[DEBUG]   Subregion 0: 0x80000000 0x300000
[DEBUG]   Subregion 1: 0x80300000 0x100000
[DEBUG]   Subregion 2: 0x80400000 0x400000
[DEBUG]  Normal boot
[INFO ]  CBFS: Found 'fallback/postcar' @0x40380 size 0x57b8 in mcache @0xfeff102c
[DEBUG]  Loading module at 0x7ffd0000 with entry 0x7ffd0031. filesize: 0x5408 memsize: 0xb758
[DEBUG]  Processing 220 relocs. Offset value of 0x7dfd0000
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 2 ms

[NOTE ]  coreboot-24.05-84-g345f48275a2a-MrChromebox-2405.0 Sat Jun 15 17:30:29 UTC 2024 x86_32 postcar starting (log level: 7)...
[DEBUG]  Normal boot
[DEBUG]  FMAP: area COREBOOT found @ 554200 (2801152 bytes)
[INFO ]  CBFS: Found 'fallback/ramstage' @0x1d1c0 size 0x1e97c in mcache @0x7fffe9fc
[DEBUG]  Loading module at 0x7fe81000 with entry 0x7fe81000. filesize: 0x3e038 memsize: 0x14d230
[DEBUG]  Processing 4214 relocs. Offset value of 0x7be81000
[DEBUG]  BS: postcar times (exec / console): total (unknown) / 0 ms

[NOTE ]  coreboot-24.05-84-g345f48275a2a-MrChromebox-2405.0 Sat Jun 15 17:30:29 UTC 2024 x86_32 ramstage starting (log level: 7)...
[DEBUG]  Normal boot
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 00000000 enabled
[DEBUG]  DOMAIN: 00000000 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 00
[DEBUG]  PCI: 00:00:00.0 [8086/0104] enabled
[DEBUG]  PCI: 00:00:01.0 [8086/0101] disabled
[DEBUG]  PCI: 00:00:02.0 [8086/0126] enabled
[DEBUG]  PCI: 00:00:04.0 [8086/0103] disabled
[DEBUG]  PCI: 00:00:14.0: Disabling device
[DEBUG]  PCI: 00:00:16.0 [8086/1c3a] enabled
[DEBUG]  PCI: 00:00:16.1: Disabling device
[DEBUG]  PCI: 00:00:16.1 [8086/1c3b] disabled No operations
[DEBUG]  PCI: 00:00:16.2: Disabling device
[DEBUG]  PCI: 00:00:16.2 [8086/1c3c] disabled No operations
[DEBUG]  PCI: 00:00:16.3: Disabling device
[DEBUG]  PCI: 00:00:16.3 [8086/1c3d] disabled No operations
[DEBUG]  PCI: 00:00:19.0: Disabling device
[DEBUG]  PCI: 00:00:1a.0 [8086/1c2d] enabled
[DEBUG]  PCI: 00:00:1b.0 [8086/1c20] enabled
[DEBUG]  PCI: 00:00:1c.0: Found a downstream device
[DEBUG]  PCI: 00:00:1c.0 [8086/1c10] enabled
[DEBUG]  PCI: 00:00:1c.1: No downstream device
[DEBUG]  PCI: 00:00:1c.1: Disabling device
[DEBUG]  PCI: 00:00:1c.2: Found a downstream device
[DEBUG]  PCI: 00:00:1c.2 [8086/1c14] enabled
[DEBUG]  PCI: 00:00:1c.3: Found a downstream device
[DEBUG]  PCI: 00:00:1c.3 [8086/1c16] enabled
[DEBUG]  PCI: 00:00:1c.4: No downstream device
[DEBUG]  PCI: 00:00:1c.4: Disabling device
[DEBUG]  PCI: 00:00:1c.4: check set enabled
[DEBUG]  PCI: 00:00:1c.5: No downstream device
[DEBUG]  PCI: 00:00:1c.5: Disabling device
[DEBUG]  PCI: 00:00:1c.6: No downstream device
[DEBUG]  PCI: 00:00:1c.6: Disabling device
[DEBUG]  PCI: 00:00:1c.7: No downstream device
[DEBUG]  PCI: 00:00:1c.7: Disabling device
[DEBUG]  PCI: 00:00:1d.0 [8086/1c26] enabled
[DEBUG]  PCI: 00:00:1e.0: Disabling device
[DEBUG]  PCI: 00:00:1e.0 [8086/2448] disabled
[DEBUG]  PCI: 00:00:1f.0 [8086/1c49] enabled
[DEBUG]  PCI: 00:00:1f.2 [8086/1c01] enabled
[DEBUG]  PCI: 00:00:1f.3 [8086/1c22] enabled
[DEBUG]  PCI: 00:00:1f.5: Disabling device
[DEBUG]  PCI: 00:00:1f.5 [8086/1c09] disabled No operations
[DEBUG]  PCI: 00:00:1f.6 [8086/1c24] enabled
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:00:01.1
[WARN ]  PCI: 00:00:01.2
[WARN ]  PCI: 00:00:06.0
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:00:1c.0 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 01
[DEBUG]  PCI: 00:01:00.0 [168c/0030] enabled
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L0s and L1
[DEBUG]  PCI: 00:01:00.0: No LTR support
[INFO ]  PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:1c.0 finished in 0 msecs
[DEBUG]  PCI: 00:00:1c.2 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 02
[DEBUG]  PCI: 00:02:00.0 [1b73/1100] enabled
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled None
[DEBUG]  PCI: 00:02:00.0: No LTR support
[INFO ]  PCI: 00:00:1c.2: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:1c.2 finished in 0 msecs
[DEBUG]  PCI: 00:00:1c.3 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 03
[DEBUG]  PCI: 00:03:00.0 [10ec/8168] enabled
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L1
[DEBUG]  PCI: 00:03:00.0: No LTR support
[INFO ]  PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:1c.3 finished in 0 msecs
[DEBUG]  PCI: 00:00:1f.0 scanning...
[DEBUG]  PNP: 002e.0 disabled
[DEBUG]  PNP: 002e.1 enabled
[DEBUG]  PNP: 002e.4 enabled
[DEBUG]  PNP: 002e.7 enabled
[DEBUG]  PNP: 002e.5 enabled
[DEBUG]  PNP: 002e.6 enabled
[DEBUG]  PNP: 002e.a disabled
[INFO ]  Found TPM 1.2 SLB9635 TT 1.2 (0x000b) by Infineon (0x15d1)
[DEBUG]  PNP: 0c31.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:00:1f.0 finished in 0 msecs
[DEBUG]  PCI: 00:00:1f.3 scanning...
[DEBUG]  scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
[DEBUG]  scan_bus: bus DOMAIN: 00000000 finished in 1 msecs
[DEBUG]  scan_bus: bus Root Device finished in 1 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 0 ms
[DEBUG]  found VGA at PCI: 00:00:02.0
[DEBUG]  Setting up VGA for PCI: 00:00:02.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[DEBUG]  Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
[DEBUG]  TOUUD 0x278e00000 TOLUD 0x86a00000 TOM 0x200000000
[DEBUG]  MEBASE 0x1ff800000
[DEBUG]  IGD decoded, subtracting 96M UMA and 2M GTT
[DEBUG]  TSEG base 0x80000000 size 8M
[INFO ]  Available memory below 4GB: 2048M
[INFO ]  Available memory above 4GB: 6030M
[INFO ]  Done reading resources.
[INFO ]  === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
[DEBUG]   PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]   PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 00:01:00.0 10 *  [0x0 - 0x1ffff] mem
[DEBUG]    PCI: 00:01:00.0 30 *  [0x20000 - 0x2ffff] mem
[DEBUG]   PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]   PCI: 00:00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 00:02:00.0 10 *  [0x0 - 0xffff] mem
[DEBUG]    PCI: 00:02:00.0 18 *  [0x10000 - 0x10fff] mem
[DEBUG]    PCI: 00:02:00.0 20 *  [0x11000 - 0x11fff] mem
[DEBUG]   PCI: 00:00:1c.2 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 00:03:00.0 10 *  [0x0 - 0xff] io
[DEBUG]   PCI: 00:00:1c.3 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]   PCI: 00:00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]    PCI: 00:03:00.0 20 *  [0x0 - 0x3fff] prefmem
[DEBUG]    PCI: 00:03:00.0 18 *  [0x4000 - 0x4fff] prefmem
[DEBUG]   PCI: 00:00:1c.3 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[INFO ]  === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.0 10000200 base 00001600 limit 000016fb io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.1 60 base 000002f8 limit 000002ff io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.4 60 base 00000700 limit 00000707 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.4 62 base 00000710 limit 00000713 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.7 60 base 00000720 limit 00000720 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.7 62 base 00000730 limit 00000737 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
[INFO ]   DOMAIN: 00000000: Resource ranges:
[INFO ]   * Base: 1000, Size: 600, Tag: 100
[INFO ]   * Base: 16fc, Size: e904, Tag: 100
[DEBUG]    PCI: 00:00:1c.3 1c *  [0x2000 - 0x2fff] limit: 2fff io
[DEBUG]    PCI: 00:00:02.0 20 *  [0x1000 - 0x103f] limit: 103f io
[DEBUG]    PCI: 00:00:1f.2 20 *  [0x1040 - 0x105f] limit: 105f io
[DEBUG]    PCI: 00:00:1f.2 10 *  [0x1060 - 0x1067] limit: 1067 io
[DEBUG]    PCI: 00:00:1f.2 18 *  [0x1068 - 0x106f] limit: 106f io
[DEBUG]    PCI: 00:00:1f.2 14 *  [0x1070 - 0x1073] limit: 1073 io
[DEBUG]    PCI: 00:00:1f.2 1c *  [0x1074 - 0x1077] limit: 1077 io
[DEBUG]  DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: fdffffff
[DEBUG]  DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 05 base 100000000 limit 278dfffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 06 base 80000000 limit 869fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 09 base 20000000 limit 201fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:00.0 0a base 40000000 limit 401fffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
[DEBUG]   avoid_fixed_resources: PCI: 00:00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
[DEBUG]   avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
[INFO ]   DOMAIN: 00000000: Resource ranges:
[INFO ]   * Base: 86a00000, Size: 69600000, Tag: 200
[INFO ]   * Base: f4000000, Size: a000000, Tag: 200
[INFO ]   * Base: 278e00000, Size: d87200000, Tag: 200
[DEBUG]    PCI: 00:00:02.0 18 *  [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
[DEBUG]    PCI: 00:00:02.0 10 *  [0x86c00000 - 0x86ffffff] limit: 86ffffff mem
[DEBUG]    PCI: 00:00:1c.0 20 *  [0x86a00000 - 0x86afffff] limit: 86afffff mem
[DEBUG]    PCI: 00:00:1c.2 20 *  [0x86b00000 - 0x86bfffff] limit: 86bfffff mem
[DEBUG]    PCI: 00:00:1c.3 24 *  [0x87000000 - 0x870fffff] limit: 870fffff prefmem
[DEBUG]    PCI: 00:00:1b.0 10 *  [0x87100000 - 0x87103fff] limit: 87103fff mem
[DEBUG]    PCI: 00:00:1f.6 10 *  [0x87104000 - 0x87104fff] limit: 87104fff mem
[DEBUG]    PCI: 00:00:1f.2 24 *  [0x87105000 - 0x871057ff] limit: 871057ff mem
[DEBUG]    PCI: 00:00:1a.0 10 *  [0x87106000 - 0x871063ff] limit: 871063ff mem
[DEBUG]    PCI: 00:00:1d.0 10 *  [0x87107000 - 0x871073ff] limit: 871073ff mem
[DEBUG]    PCI: 00:00:1f.3 10 *  [0x87108000 - 0x871080ff] limit: 871080ff mem
[DEBUG]    PCI: 00:00:16.0 10 *  [0x87109000 - 0x8710900f] limit: 8710900f mem
[DEBUG]  DOMAIN: 00000000 mem: base: 80000000 size: 0 align: 0 gran: 0 limit: fdffffff done
[DEBUG]  DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: fffffffff done
[DEBUG]    PCI: 00:01:00.0 10 *  [0x86a00000 - 0x86a1ffff] limit: 86a1ffff mem
[DEBUG]    PCI: 00:01:00.0 30 *  [0x86a20000 - 0x86a2ffff] limit: 86a2ffff mem
[DEBUG]    PCI: 00:02:00.0 10 *  [0x86b00000 - 0x86b0ffff] limit: 86b0ffff mem
[DEBUG]    PCI: 00:02:00.0 18 *  [0x86b10000 - 0x86b10fff] limit: 86b10fff mem
[DEBUG]    PCI: 00:02:00.0 20 *  [0x86b11000 - 0x86b11fff] limit: 86b11fff mem
[DEBUG]    PCI: 00:03:00.0 10 *  [0x2000 - 0x20ff] limit: 20ff io
[DEBUG]    PCI: 00:03:00.0 18 *  [0x87004000 - 0x87004fff] limit: 87004fff prefmem
[DEBUG]    PCI: 00:03:00.0 20 *  [0x87000000 - 0x87003fff] limit: 87003fff prefmem
[INFO ]  === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
[DEBUG]  PCI: 00:00:02.0 10 <- [0x0000000086c00000 - 0x0000000086ffffff] size 0x00400000 gran 0x16 mem64
[DEBUG]  PCI: 00:00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG]  PCI: 00:00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
[DEBUG]  PCI: 00:00:16.0 10 <- [0x0000000087109000 - 0x000000008710900f] size 0x00000010 gran 0x04 mem64
[DEBUG]  PCI: 00:00:1a.0 10 <- [0x0000000087106000 - 0x00000000871063ff] size 0x00000400 gran 0x0a mem
[DEBUG]  PCI: 00:00:1b.0 10 <- [0x0000000087100000 - 0x0000000087103fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio
[DEBUG]  PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem
[DEBUG]  PCI: 00:00:1c.0 20 <- [0x0000000086a00000 - 0x0000000086afffff] size 0x00100000 gran 0x14 seg 00 bumem
[DEBUG]  PCI: 00:01:00.0 10 <- [0x0000000086a00000 - 0x0000000086a1ffff] size 0x00020000 gran 0x11 mem64
[DEBUG]  PCI: 00:01:00.0 30 <- [0x0000000086a20000 - 0x0000000086a2ffff] size 0x00010000 gran 0x10 romem
[DEBUG]  PCI: 00:00:1c.2 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio
[DEBUG]  PCI: 00:00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem
[DEBUG]  PCI: 00:00:1c.2 20 <- [0x0000000086b00000 - 0x0000000086bfffff] size 0x00100000 gran 0x14 seg 00 bumem
[DEBUG]  PCI: 00:02:00.0 10 <- [0x0000000086b00000 - 0x0000000086b0ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:02:00.0 18 <- [0x0000000086b10000 - 0x0000000086b10fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:02:00.0 20 <- [0x0000000086b11000 - 0x0000000086b11fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:00:1c.3 1c <- [0x0000000000002000 - 0x0000000000002fff] size 0x00001000 gran 0x0c seg 00 buio
[DEBUG]  PCI: 00:00:1c.3 24 <- [0x0000000087000000 - 0x00000000870fffff] size 0x00100000 gran 0x14 seg 00 buprefmem
[DEBUG]  PCI: 00:00:1c.3 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bumem
[DEBUG]  PCI: 00:03:00.0 10 <- [0x0000000000002000 - 0x00000000000020ff] size 0x00000100 gran 0x08 io
[DEBUG]  PCI: 00:03:00.0 18 <- [0x0000000087004000 - 0x0000000087004fff] size 0x00001000 gran 0x0c prefmem64
[DEBUG]  PCI: 00:03:00.0 20 <- [0x0000000087000000 - 0x0000000087003fff] size 0x00004000 gran 0x0e prefmem64
[DEBUG]  PCI: 00:00:1d.0 10 <- [0x0000000087107000 - 0x00000000871073ff] size 0x00000400 gran 0x0a mem
[DEBUG]  PNP: 002e.1 60 <- [0x00000000000002f8 - 0x00000000000002ff] size 0x00000008 gran 0x03 io
[DEBUG]  PNP: 002e.1 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq
[DEBUG]  PNP: 002e.4 60 <- [0x0000000000000700 - 0x0000000000000707] size 0x00000008 gran 0x03 io
[DEBUG]  PNP: 002e.4 62 <- [0x0000000000000710 - 0x0000000000000713] size 0x00000004 gran 0x02 io
[NOTE ]  PNP: 002e.4 70 irq size: 0x0000000001 not assigned in devicetree
[NOTE ]  PNP: 002e.4 f4 irq size: 0x0000000001 not assigned in devicetree
[NOTE ]  PNP: 002e.4 fa irq size: 0x0000000001 not assigned in devicetree
[DEBUG]  PNP: 002e.7 60 <- [0x0000000000000720 - 0x0000000000000720] size 0x00000001 gran 0x00 io
[DEBUG]  PNP: 002e.7 62 <- [0x0000000000000730 - 0x0000000000000737] size 0x00000008 gran 0x03 io
[DEBUG]  PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
[DEBUG]  PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
[DEBUG]  PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
[DEBUG]  PNP: 002e.6 70 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
[DEBUG]  PCI: 00:00:1f.2 10 <- [0x0000000000001060 - 0x0000000000001067] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:00:1f.2 14 <- [0x0000000000001070 - 0x0000000000001073] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:00:1f.2 18 <- [0x0000000000001068 - 0x000000000000106f] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:00:1f.2 1c <- [0x0000000000001074 - 0x0000000000001077] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:00:1f.2 20 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 00:00:1f.2 24 <- [0x0000000087105000 - 0x00000000871057ff] size 0x00000800 gran 0x0b mem
[DEBUG]  PCI: 00:00:1f.3 10 <- [0x0000000087108000 - 0x00000000871080ff] size 0x00000100 gran 0x08 mem64
[DEBUG]  PCI: 00:00:1f.6 10 <- [0x0000000087104000 - 0x0000000087104fff] size 0x00001000 gran 0x0c mem64
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 1 / 1 ms
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00:00.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:00.0 cmd <- 06
[DEBUG]  PCI: 00:00:02.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:02.0 cmd <- 03
[DEBUG]  PCI: 00:00:16.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:16.0 cmd <- 02
[DEBUG]  PCI: 00:00:1a.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1a.0 cmd <- 102
[DEBUG]  PCI: 00:00:1b.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1b.0 cmd <- 102
[DEBUG]  PCI: 00:00:1c.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:1c.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1c.0 cmd <- 106
[DEBUG]  PCI: 00:00:1c.2 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:1c.2 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1c.2 cmd <- 106
[DEBUG]  PCI: 00:00:1c.3 bridge ctrl <- 0013
[DEBUG]  PCI: 00:00:1c.3 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1c.3 cmd <- 107
[DEBUG]  PCI: 00:00:1d.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1d.0 cmd <- 102
[DEBUG]  PCI: 00:00:1f.0 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1f.0 cmd <- 107
[DEBUG]  PCI: 00:00:1f.2 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1f.2 cmd <- 03
[DEBUG]  PCI: 00:00:1f.3 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1f.3 cmd <- 103
[DEBUG]  PCI: 00:00:1f.6 subsystem <- 1ae0/c000
[DEBUG]  PCI: 00:00:1f.6 cmd <- 02
[DEBUG]  PCI: 00:01:00.0 cmd <- 02
[DEBUG]  PCI: 00:02:00.0 cmd <- 02
[DEBUG]  PCI: 00:03:00.0 cmd <- 03
[INFO ]  done.
[INFO ]  Initializing devices...
[DEBUG]  CPU_CLUSTER: 0 init
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
[DEBUG]  0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0
[DEBUG]  0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1
[DEBUG]  0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0
[DEBUG]  0x0000000100000000 - 0x0000000278dfffff size 0x178e00000 type 6
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 4/4.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1
[DEBUG]  MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6
[DEBUG]  MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[DEBUG]  CPU has 2 cores, 4 threads enabled.
[DEBUG]  Setting up SMI for CPU
[INFO ]  Will perform SMM setup.
[DEBUG]  microcode: sig=0x206a7 pf=0x10 revision=0x2f
[DEBUG]  FMAP: area COREBOOT found @ 554200 (2801152 bytes)
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0x16980 size 0x6800 in mcache @0x7fffe9cc
[INFO ]  CPU: Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  CPU: APIC: 00 enabled
[DEBUG]  CPU: APIC: 01 enabled
[DEBUG]  CPU: APIC: 02 enabled
[DEBUG]  CPU: APIC: 03 enabled
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 16 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 3 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[DEBUG]  Waiting for SIPI to complete...
[INFO ]  LAPIC 0x1 in XAPIC mode.
[DEBUG]  done.
[INFO ]  AP: slot 1 apic_id 1, MCU rev: 0x0000002f
[INFO ]  LAPIC 0x3 in XAPIC mode.
[INFO ]  LAPIC 0x2 in XAPIC mode.
[INFO ]  AP: slot 3 apic_id 3, MCU rev: 0x0000002f
[INFO ]  AP: slot 2 apic_id 2, MCU rev: 0x0000002f
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG]  Processing 9 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x80001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x7fea1f88
[DEBUG]  Installing permanent SMM handler to 0x80000000
[DEBUG]  HANDLER      [0x802fb000-0x802ff4c8]

[DEBUG]  CPU 0
[DEBUG]    ss0        [0x802fac00-0x802fb000]
[DEBUG]    stub0      [0x802f3000-0x802f31a0]

[DEBUG]  CPU 1
[DEBUG]    ss1        [0x802fa800-0x802fac00]
[DEBUG]    stub1      [0x802f2c00-0x802f2da0]

[DEBUG]  CPU 2
[DEBUG]    ss2        [0x802fa400-0x802fa800]
[DEBUG]    stub2      [0x802f2800-0x802f29a0]

[DEBUG]  CPU 3
[DEBUG]    ss3        [0x802fa000-0x802fa400]
[DEBUG]    stub3      [0x802f2400-0x802f25a0]

[DEBUG]  stacks       [0x80000000-0x80001000]
[DEBUG]  Loading module at 0x802fb000 with entry 0x802fbbdd. filesize: 0x4390 memsize: 0x44c8
[DEBUG]  Processing 260 relocs. Offset value of 0x802fb000
[DEBUG]  FMAP: area SMMSTORE found @ 510000 (262144 bytes)
[INFO ]  Manufacturer: ef
[INFO ]  SF: Detected ef 4017 with sector size 0x1000, total 0x800000
[DEBUG]  smm store: 4 # blocks with size 0x10000
[DEBUG]  Loading module at 0x802f3000 with entry 0x802f3000. filesize: 0x1a0 memsize: 0x1a0
[DEBUG]  Processing 9 relocs. Offset value of 0x802f3000
[DEBUG]  smm_module_setup_stub: stack_top = 0x80001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x300000
[DEBUG]  SMM Module: placing smm entry code at 802f2c00,  cpu # 0x1
[DEBUG]  SMM Module: placing smm entry code at 802f2800,  cpu # 0x2
[DEBUG]  SMM Module: placing smm entry code at 802f2400,  cpu # 0x3
[DEBUG]  SMM Module: stub loaded at 802f3000. Will call 0x802fbbdd
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb000, cpu = 0
[DEBUG]  In relocation handler: cpu 0
[DEBUG]  New SMBASE=0x802eb000 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eac00, cpu = 1
[DEBUG]  In relocation handler: cpu 1
[DEBUG]  New SMBASE=0x802eac00 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea400, cpu = 3
[DEBUG]  In relocation handler: cpu 3
[DEBUG]  New SMBASE=0x802ea400 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea800, cpu = 2
[DEBUG]  In relocation handler: cpu 2
[DEBUG]  New SMBASE=0x802ea800 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 206a7
[DEBUG]  CPU: family 06, model 2a, stepping 07
[INFO ]  CPU: Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz.
[INFO ]  CPU: cpuid(1) 0x206a7
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL already locked
[INFO ]  APIC: 00: PP0 current limit not set in devicetree
[INFO ]  APIC: 00: PP0 PSI0 not set in devicetree
[INFO ]  APIC: 00: PP0 PSI1 not set in devicetree
[INFO ]  APIC: 00: PP0 PSI2 not set in devicetree
[INFO ]  APIC: 00: PP1 current limit not set in devicetree
[INFO ]  APIC: 00: PP1 PSI0 not set in devicetree
[INFO ]  APIC: 00: PP1 PSI1 not set in devicetree
[INFO ]  APIC: 00: PP1 PSI2 not set in devicetree
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 2500
[INFO ]  Turbo is available but hidden
[INFO ]  Turbo is available and visible
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #1
[INFO ]  Initializing CPU #3
[INFO ]  Initializing CPU #2
[DEBUG]  CPU: vendor Intel device 206a7
[DEBUG]  CPU: family 06, model 2a, stepping 07
[DEBUG]  CPU: vendor Intel device 206a7
[DEBUG]  CPU: family 06, model 2a, stepping 07
[DEBUG]  CPU: vendor Intel device 206a7
[DEBUG]  CPU: family 06, model 2a, stepping 07
[INFO ]  CPU: Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz.
[INFO ]  CPU: cpuid(1) 0x206a7
[INFO ]  CPU: Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz.
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[INFO ]  CPU: cpuid(1) 0x206a7
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[DEBUG]  IA32_FEATURE_CONTROL already locked
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[INFO ]  CPU: Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz.
[DEBUG]  IA32_FEATURE_CONTROL already locked
[DEBUG]  cpu: energy policy set to 6
[INFO ]  CPU: cpuid(1) 0x206a7
[INFO ]  CPU: AES supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 2500
[INFO ]  CPU #3 initialized
[DEBUG]  model_x06ax: frequency set to 2500
[INFO ]  CPU #2 initialized
[DEBUG]  IA32_FEATURE_CONTROL already locked; VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL already locked
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 2500
[INFO ]  CPU #1 initialized
[INFO ]  bsp_do_flight_plan done after 11 msecs.
[DEBUG]  SMI_STS: 
[DEBUG]  GPE0_STS: GPIO15 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 
[DEBUG]  ALT_GP_SMI_STS: GPI15 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
[DEBUG]  TCO_STS: 
[DEBUG]  Locking SMM.
[DEBUG]  CPU_CLUSTER: 0 init finished in 23 msecs
[DEBUG]  PCI: 00:00:00.0 init
[DEBUG]  Disabling PEG12.
[DEBUG]  Disabling PEG11.
[DEBUG]  Disabling PEG10.
[DEBUG]  Disabling Device 4.
[DEBUG]  Disabling PEG60.
[DEBUG]  Disabling Device 7.
[DEBUG]  Disabling PEG IO clock.
[DEBUG]  Set BIOS_RESET_CPL
[DEBUG]  CPU TDP: 35 Watts
[DEBUG]  PCI: 00:00:00.0 init finished in 1 msecs
[DEBUG]  PCI: 00:00:02.0 init
[INFO ]  CBFS: Found 'vbt.bin' @0x3f8c0 size 0x578 in mcache @0x7fffeaf4
[INFO ]  Found a VBT of 4284 bytes
[INFO ]  GMA: Found VBT in CBFS
[INFO ]  GMA: Found valid VBT in CBFS
[DEBUG]  GT Power Management Init
[DEBUG]  SNB GT2 Power Meter Weights
[DEBUG]  GT Power Management Init (post VBIOS)
[DEBUG]  PCI: 00:00:02.0 init finished in 505 msecs
[DEBUG]  PCI: 00:00:16.0 init
[DEBUG]  ME: FW Partition Table      : OK
[DEBUG]  ME: Bringup Loader Failure  : NO
[DEBUG]  ME: Firmware Init Complete  : YES
[DEBUG]  ME: Manufacturing Mode      : NO
[DEBUG]  ME: Boot Options Present    : NO
[DEBUG]  ME: Update In Progress      : NO
[DEBUG]  ME: Current Working State   : Normal
[DEBUG]  ME: Current Operation State : M0 with UMA
[DEBUG]  ME: Current Operation Mode  : Normal
[DEBUG]  ME: Error Code              : No Error
[DEBUG]  ME: Progress Phase          : Host Communication
[DEBUG]  ME: Power Management Event  : Pseudo-global reset
[DEBUG]  ME: Progress Phase State    : Host communication established
[NOTE ]  ME: BIOS path: Normal
[DEBUG]  ME: me_state=0, me_state_prev=0
[DEBUG]  ME: Extend SHA-256: f7989d5d624d091ea3f0485fecd9e745f59ce47189f80379508c8fdf373c15ce
[INFO ]  ME: Firmware Version 7.1.1142.30 (code) 7.1.1142.30 (recovery)
[DEBUG]  ME Capability: Full Network manageability     : disabled
[DEBUG]  ME Capability: Regular Network manageability  : disabled
[DEBUG]  ME Capability: Manageability                  : disabled
[DEBUG]  ME Capability: Small business technology      : disabled
[DEBUG]  ME Capability: Level III manageability        : disabled
[DEBUG]  ME Capability: IntelR Anti-Theft (AT)         : disabled
[DEBUG]  ME Capability: IntelR Capability Licensing Service (CLS) : enabled
[DEBUG]  ME Capability: IntelR Power Sharing Technology (MPC) : enabled
[DEBUG]  ME Capability: ICC Over Clocking              : enabled
[DEBUG]  ME Capability: Protected Audio Video Path (PAVP) : disabled
[DEBUG]  ME Capability: IPV6                           : disabled
[DEBUG]  ME Capability: KVM Remote Control (KVM)       : disabled
[DEBUG]  ME Capability: Outbreak Containment Heuristic (OCH) : disabled
[DEBUG]  ME Capability: Virtual LAN (VLAN)             : disabled
[DEBUG]  ME Capability: TLS                            : disabled
[DEBUG]  ME Capability: Wireless LAN (WLAN)            : disabled
[DEBUG]  PCI: 00:00:16.0 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1a.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:00:1a.0 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1b.0 init
[DEBUG]  Azalia: base = 0x87100000
[DEBUG]  Azalia: codec_mask = 09
[DEBUG]  azalia_audio: Initializing codec #3
[DEBUG]  azalia_audio: codec viddid: 80862805
[DEBUG]  azalia_audio: verb_size: 16
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  azalia_audio: Initializing codec #0
[DEBUG]  azalia_audio: codec viddid: 10134210
[DEBUG]  azalia_audio: verb_size: 28
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  PCI: 00:00:1b.0 init finished in 3 msecs
[DEBUG]  PCI: 00:00:1c.0 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:00:1c.0 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1c.2 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:00:1c.2 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1c.3 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:00:1c.3 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1d.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:00:1d.0 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1f.0 init
[DEBUG]  pch: lpc_init
[INFO ]  PCH: detected HM65, device id: 0x1c49, rev id 0x5
[DEBUG]  IOAPIC: Initializing IOAPIC at fec00000
[DEBUG]  IOAPIC: ID = 0x00
[DEBUG]  IOAPIC: 24 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at fec00000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[INFO ]  Set power state keep after power failure.
[INFO ]  NMI sources disabled.
[DEBUG]  CougarPoint PM init
[DEBUG]  RTC: failed = 0x0
[DEBUG]  RTC Init
[DEBUG]  apm_control: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  pch_spi_init
[DEBUG]  PCI: 00:00:1f.0 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1f.2 init
[DEBUG]  SATA: Initializing...
[DEBUG]  SATA: Controller in AHCI mode.
[DEBUG]  ABAR: 0x87105000
[DEBUG]  PCI: 00:00:1f.2 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1f.3 init
[DEBUG]  PCI: 00:00:1f.3 init finished in 0 msecs
[DEBUG]  PCI: 00:00:1f.6 init
[DEBUG]  PCI: 00:00:1f.6 init finished in 0 msecs
[DEBUG]  PCI: 00:01:00.0 init
[DEBUG]  PCI: 00:01:00.0 init finished in 0 msecs
[DEBUG]  PCI: 00:02:00.0 init
[DEBUG]  PCI: 00:02:00.0 init finished in 0 msecs
[DEBUG]  PCI: 00:03:00.0 init
[DEBUG]  PCI: 00:03:00.0 init finished in 0 msecs
[DEBUG]  PNP: 002e.1 init
[DEBUG]  PNP: 002e.1 init finished in 0 msecs
[DEBUG]  PNP: 002e.4 init
[DEBUG]  PNP: 002e.4 init finished in 0 msecs
[DEBUG]  PNP: 002e.7 init
[DEBUG]  PNP: 002e.7 init finished in 0 msecs
[DEBUG]  PNP: 002e.5 init
[DEBUG]  PNP: 002e.5 init finished in 0 msecs
[DEBUG]  PNP: 002e.6 init
[DEBUG]  PNP: 002e.6 init finished in 0 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 534 / 1 ms
[DEBUG]  TPM: Startup
[DEBUG]  TPM: command 0x99 returned 0x0
[DEBUG]  TPM: Asserting physical presence
[DEBUG]  TPM: command 0x4000000a returned 0x0
[INFO ]  TPM: setup succeeded
[DEBUG]  BS: BS_DEV_INIT exit times (exec / console): 51 / 0 ms
[INFO ]  Finalize devices...
[DEBUG]  PCI: 00:00:1f.0 final
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[INFO ]  Devices finalized
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x3cd40 size 0x2b44 in mcache @0x7fffeac8
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 7fe30000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  ACPI:    * FACP
[DEBUG]  ACPI: added table 1/32, length now 44
[DEBUG]  Found 1 CPU(s) with 4 core(s) each.
[DEBUG]  Supported C-states:  C0 C1 C1E C3 C6 C7 C7S
[DEBUG]  PSS: 2501MHz power 35000 control 0x1f00 status 0x1f00
[DEBUG]  PSS: 2500MHz power 35000 control 0x1900 status 0x1900
[DEBUG]  PSS: 2000MHz power 26404 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 20160 control 0x1000 status 0x1000
[DEBUG]  PSS: 1200MHz power 14397 control 0xc00 status 0xc00
[DEBUG]  PSS: 800MHz power 9139 control 0x800 status 0x800
[DEBUG]  Advertising ACPI C State type C1 as CPU C3
[DEBUG]  Advertising ACPI C State type C2 as CPU C6
[DEBUG]  Advertising ACPI C State type C3 as CPU C7
[DEBUG]  PSS: 2501MHz power 35000 control 0x1f00 status 0x1f00
[DEBUG]  PSS: 2500MHz power 35000 control 0x1900 status 0x1900
[DEBUG]  PSS: 2000MHz power 26404 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 20160 control 0x1000 status 0x1000
[DEBUG]  PSS: 1200MHz power 14397 control 0xc00 status 0xc00
[DEBUG]  PSS: 800MHz power 9139 control 0x800 status 0x800
[DEBUG]  Advertising ACPI C State type C1 as CPU C3
[DEBUG]  Advertising ACPI C State type C2 as CPU C6
[DEBUG]  Advertising ACPI C State type C3 as CPU C7
[DEBUG]  PSS: 2501MHz power 35000 control 0x1f00 status 0x1f00
[DEBUG]  PSS: 2500MHz power 35000 control 0x1900 status 0x1900
[DEBUG]  PSS: 2000MHz power 26404 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 20160 control 0x1000 status 0x1000
[DEBUG]  PSS: 1200MHz power 14397 control 0xc00 status 0xc00
[DEBUG]  PSS: 800MHz power 9139 control 0x800 status 0x800
[DEBUG]  Advertising ACPI C State type C1 as CPU C3
[DEBUG]  Advertising ACPI C State type C2 as CPU C6
[DEBUG]  Advertising ACPI C State type C3 as CPU C7
[DEBUG]  PSS: 2501MHz power 35000 control 0x1f00 status 0x1f00
[DEBUG]  PSS: 2500MHz power 35000 control 0x1900 status 0x1900
[DEBUG]  PSS: 2000MHz power 26404 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 20160 control 0x1000 status 0x1000
[DEBUG]  PSS: 1200MHz power 14397 control 0xc00 status 0xc00
[DEBUG]  PSS: 800MHz power 9139 control 0x800 status 0x800
[DEBUG]  Advertising ACPI C State type C1 as CPU C3
[DEBUG]  Advertising ACPI C State type C2 as CPU C6
[DEBUG]  Advertising ACPI C State type C3 as CPU C7
[DEBUG]  PCI space above 4GB MMIO is at 0x278e00000, len = 0xd87200000
[DEBUG]  Generating ACPI PIRQ entries
[DEBUG]  PPI: Pending OS request: 0x0 (0x0)
[DEBUG]  PPI: OS response: CMD 0xd77ab4ba = 0x0
[INFO ]  \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
[DEBUG]  ACPI:    * SSDT
[DEBUG]  ACPI: added table 2/32, length now 52
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 60
[DEBUG]  TCPA log created at 0x7fe20000
[DEBUG]  ACPI:    * TCPA
[DEBUG]  ACPI: added table 4/32, length now 68
[DEBUG]  IOAPIC: 24 interrupts
[DEBUG]  ACPI:    * APIC
[DEBUG]  ACPI: added table 5/32, length now 76
[DEBUG]  current = 7fe347a0
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 6/32, length now 84
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 18400 bytes.
[DEBUG]  smbios_write_tables: 7fe18000
[DEBUG]  BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-2405.0'
[DEBUG]  FMAP: area RO_VPD found @ 550000 (16384 bytes)
[WARN ]  RO_VPD is uninitialized or empty.
[WARN ]  init_vpd_rdev: No RW_VPD FMAP section.
[INFO ]  Create SMBIOS type 16
[INFO ]  Create SMBIOS type 17
[INFO ]  Create SMBIOS type 20
[DEBUG]  SMBIOS tables: 773 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 3ff9
[DEBUG]  Writing coreboot table at 0x7fe54000
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG]   3. 0000000000100000-000000001fffffff: RAM
[DEBUG]   4. 0000000020000000-00000000201fffff: RESERVED
[DEBUG]   5. 0000000020200000-000000003fffffff: RAM
[DEBUG]   6. 0000000040000000-00000000401fffff: RESERVED
[DEBUG]   7. 0000000040200000-000000007fe17fff: RAM
[DEBUG]   8. 000000007fe18000-000000007fe80fff: CONFIGURATION TABLES
[DEBUG]   9. 000000007fe81000-000000007ffcefff: RAMSTAGE
[DEBUG]  10. 000000007ffcf000-000000007fffffff: CONFIGURATION TABLES
[DEBUG]  11. 0000000080000000-00000000869fffff: RESERVED
[DEBUG]  12. 00000000f0000000-00000000f3ffffff: RESERVED
[DEBUG]  13. 00000000fed40000-00000000fed44fff: RESERVED
[DEBUG]  14. 0000000100000000-0000000278dfffff: RAM
[DEBUG]  FMAP: area SMMSTORE found @ 510000 (262144 bytes)
[DEBUG]  smm store: 4 # blocks with size 0x10000
[DEBUG]  Wrote coreboot table at: 0x7fe54000, 0x450 bytes, checksum ecf
[DEBUG]  coreboot table: 1128 bytes.
[DEBUG]  IMD ROOT    0. 0x7ffff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x7fffe000 0x00001000
[DEBUG]  CONSOLE     2. 0x7ffde000 0x00020000
[DEBUG]  TIME STAMP  3. 0x7ffdd000 0x00000910
[DEBUG]  MEM INFO    4. 0x7ffdc000 0x00000f48
[DEBUG]  AFTER CAR   5. 0x7ffcf000 0x0000d000
[DEBUG]  RAMSTAGE    6. 0x7fe80000 0x0014f000
[DEBUG]  SMM BACKUP  7. 0x7fe70000 0x00010000
[DEBUG]  SMM COMBUFFER 8. 0x7fe60000 0x00010000
[DEBUG]  IGD OPREGION 9. 0x7fe5c000 0x000030b8
[DEBUG]  COREBOOT   10. 0x7fe54000 0x00008000
[DEBUG]  ACPI       11. 0x7fe30000 0x00024000
[DEBUG]  TCPA TCGLOG12. 0x7fe20000 0x00010000
[DEBUG]  SMBIOS     13. 0x7fe18000 0x00008000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x7fffec00 0x00000400
[DEBUG]    RO MCACHE   1. 0x7fffe920 0x000002e0
[DEBUG]    FMAP        2. 0x7fffe7e0 0x00000134
[DEBUG]    ROMSTAGE    3. 0x7fffe7c0 0x00000004
[DEBUG]    ROMSTG STCK 4. 0x7fffe700 0x000000a8
[DEBUG]    ACPI GNVS   5. 0x7fffe600 0x00000100
[DEBUG]    TPM PPI     6. 0x7fffe4a0 0x0000015a
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 2 / 0 ms
[INFO ]  CBFS: Found 'fallback/payload' @0x45b80 size 0x13ed26 in mcache @0x7fffeb90
[DEBUG]  Checking segment from ROM address 0xffd99dac
[DEBUG]  Checking segment from ROM address 0xffd99dc8
[DEBUG]  Loading segment from ROM address 0xffd99dac
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xffd99de4 filesize 0x13ecee
[DEBUG]  Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x000000000013ecee
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xffd99dc8
[DEBUG]    Entry Point 0x008016b3
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 436 / 0 ms
[DEBUG]  ICH-NM10-PCH: watchdog disabled
[DEBUG]  Jumping to boot code at 0x008016b3(0x7fe54000)
MrChromebox commented 3 months ago

since you have both working/non-working setups, can you dump the info from sudo lspci -vvv -s <pci bus:device.function> for both cases? attach as files vs pasting if possible

ShapeShifter499 commented 3 months ago

@MrChromebox dump the 'working' setup from the surface pro? That doesn't use any extra pci cards, the USB 3.0 is built in there. On the Chromebox, USB devices error if they use UASP.

MrChromebox commented 3 months ago

ok, just dump it from the Chromebox then, will see if anything jumps out

ShapeShifter499 commented 3 months ago

Here are my logs, including a new third PCI card I brought for testing. But now I'm even more confused as to what is screwing up here. The Renesas based card stopped throwing errors for the UASP enabled hard drive enclosure I am using. I even tested with a high I/O load by mounting the drive and running various versions of dd if=/dev/urandom of=/mnt/test_urandom.img for a bit, I even tried three writes to different test files at the same time with dd and still no errors.

The UASP errors like the ones seen with the other two cards was the whole reason I went and tried any other cards than the Renesas card. Do you have any ideas what might have happened? The only variables here I can think of. I updated both the kernel and the coreboot build. And that I was swapping cards around, so possibly dodgy connection? Unfortunately I didn't check any lspci outputs when the Renesas card was throwing errors.

I do know that no matter how many times I tried to seat and ensure the Fresco Logic and ASMedia cards seemed well connected that I could reliably trigger those UASP errors.

uPD720202 Renesas based Mini PCIe card connected to a Mini PCIe flat ribbon extender. Included two sets of logs, 'boot2' is after a reboot command. Renesas_uPD720202-cbmem_log.txt Renesas_uPD720202-dmesg_log.txt Renesas_uPD720202-lspci.txt Renesas_uPD720202-lspci_extended.txt

Renesas_uPD720202-boot2-cbmem_log.txt Renesas_uPD720202-boot2-dmesg_log.txt Renesas_uPD720202-boot2-lspci.txt Renesas_uPD720202-boot2-lspci_extended.txt

Fresco Logic FL1100 based PCIe card connected to a PCIe 1x to Mini PCIe adapter, which is then connected to the Mini PCIe flat ribbon extender. Fresco_Logic_FL1100-cbmem_log.txt Fresco_Logic_FL1100-dmesg_log.txt Fresco_Logic_FL1100-lspci.txt Fresco_Logic_FL1100-lspci_extended.txt

ASMedia ASM1042 based PCIe card connected to a PCIe 1x to Mini PCIe adapter, which is then connected to the Mini PCIe flat ribbon extender. ASMedia_ASM1042-cbmem_log.txt ASMedia_ASM1042-dmesg_log.txt ASMedia_ASM1042-lspci.txt ASMedia_ASM1042-lspci_extended.txt

ShapeShifter499 commented 2 months ago

@MrChromebox I'm not sure if the Coreboot update happened to carry a fix, or if it was the kernel, or if simply reseating all of the connections on the board again helped.

But it's been a few days of 24/7 uptime and no UAS errors so far. I've gone back to using the uPD720202 Renesas based Mini PCIe card.

Do you have any thoughts on the matter before this gets closed?

MrChromebox commented 2 months ago

not really, if the issue comes back we'll likely need to dig into the PCI transactions to see what's happening

ShapeShifter499 commented 1 month ago

I'm going to close this. I no longer experience issues and any new UAS/UASP issues I have now appear to be related to two failing hard drives I have. The still working hard drives I have no longer crash the system when used with an enclosure that appears to properly implement UAS/UASP.

However the uPD720202 Renesas based Mini PCIe card seems to be the only card I brought that works with this system.

Anyone can reopen this if they experience issues related on this model Samsung Chromebox Stumpy