HP Elite Dragonfly can not flash firmware

[leenchan]

flashrom 1.4.0-devel on Linux 5.10.180-22627-g679a94b8d670 (x86_64) flashrom was built with LLVM Clang 17.0.0 (/mnt/host/source/src/third_party/llvm-project 98f5a340975bc00197c57e39eb4ca26e2da0e8a2), little endian Command line (10 args): /usr/sbin/flashrom -p internal --ifd -i bios -N -w coreboot_edk2-redrix-mrchromebox_20230515.rom -o /tmp/flashrom.log Acquiring lock (timeout=180 sec)... Opened file lock "/run/lock/firmware_utility_lock" Lock acquired. Initializing internal programmer /sys/class/mtd/mtd0 does not exist Found candidate at: 00000500-00000528 Found coreboot table at 0x00000500. Found candidate at: 00000000-000006e8 Found coreboot table at 0x00000000. coreboot table found at 0x7688b000. coreboot header(24) checksum: da96 table(1744) checksum: 8cb5 entries: 54 Vendor ID: Google, part ID: Redrix Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "Google" DMI string system-product-name: "Redrix" DMI string system-version: "rev3" DMI string baseboard-manufacturer: "Google" DMI string baseboard-product-name: "Redrix" DMI string baseboard-version: "rev3" Found chipset "Intel Alder Lake-P" with PCI ID 8086:51a4. Enabling flash write... BIOS_SPI_BC = 0x1900008b: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPIBAR = 0x00007cc8be721000 (phys = 0x807c8000) 0x04: 0xf000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down. Reading OPCODES... done OP Type Pre-OP op[0]: 0x01, write w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x20, write w/ addr, none op[5]: 0x9f, read w/o addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0x0b, read w/ addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0010 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000001 (FADDR) 0x0c: 0x00001f00 (DLOCK) DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, PR0_LOCKDN=1, PR1_LOCKDN=1, PR2_LOCKDN=1, PR3_LOCKDN=1, PR4_LOCKDN=1, SSEQ_LOCKDN=0 0x50: 0x000042c7 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x42, BRRA 0xc7 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x1fff0500 FREG1: BIOS region (0x00500000-0x01ffffff) is read-write. 0x5C: 0x04ff0001 FREG2: Management Engine region (0x00001000-0x004fffff) is read-only. 0x60: 0x00007fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00007fff FREG4: Platform Data region is unused. 0x68: 0x00007fff FREG5: Device Expansion region is unused. 0x6C: 0x00007fff FREG6: BIOS2 region is unused. 0x70: 0x00007fff FREG7: unknown region is unused. 0x74: 0x00007fff FREG8: EC/BMC region is unused. 0x78: 0x00007fff FREG9: unknown region is unused. 0x7C: 0x00007fff FREG10: unknown region is unused. 0x80: 0x00007fff FREG11: unknown region is unused. 0xE0: 0x00007fff FREG12: unknown region is unused. 0xE4: 0x00007fff FREG13: unknown region is unused. 0xE8: 0x00007fff FREG14: unknown region is unused. 0xEC: 0x00007fff FREG15: unknown region is unused. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. 0x84: 0x00000000 (PR0 is unused) 0x88: 0x00000000 (PR1 is unused) 0x8C: 0x00000000 (PR2 is unused) 0x90: 0x00000000 (PR3 is unused) 0x94: 0x00000000 (PR4 is unused) 0x98: 0x81a60001 GPR0: Warning: 0x00001000-0x001a6fff is read-only. At least some flash regions are write protected. For write operations, you should use a flash layout and include only writable regions. See manpage for more details. 0xa0: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0xa1: 0xfe0000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 0xa4: 0x5006 (PREOP) 0xa6: 0xb32d (OPTYPE) 0xa8: 0x05030201 (OPMENU) 0xac: 0x0bd89f20 (OPMENU+4) 0xc4: 0xf1d82084 (LVSCC) LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x00040003 FLMAP1 0x46100208 FLMAP2 0x001401b0

--- Details --- NR (Number of Regions): 16 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH/SoC Strap Length): 70 FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x100 NM (Number of Masters): 2 FMBA (Flash Master Base Address): 0x080 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0xb00

=== Component Section === FLCOMP 0x093030f6 FLILL 0xad604221 FLILL1 0xc7c4b9b7

--- Details --- Component 1 density: 32 MB Component 2 is not used. Read Clock Frequency: 100 MHz Read ID and Status Clock Freq.: 50 MHz Write and Erase Clock Freq.: 50 MHz Fast Read is supported. Fast Read Clock Frequency: 50 MHz Dual Output Fast Read Support: disabled Invalid instruction 0: 0x21 Invalid instruction 1: 0x42 Invalid instruction 2: 0x60 Invalid instruction 3: 0xad Invalid instruction 4: 0xb7 Invalid instruction 5: 0xb9 Invalid instruction 6: 0xc4 Invalid instruction 7: 0xc7

=== Region Section === FLREG0 0x00000000 FLREG1 0x1fff0500 FLREG2 0x04ff0001 FLREG3 0x00007fff FLREG4 0x00007fff FLREG5 0x00007fff FLREG6 0x00007fff FLREG7 0x00007fff FLREG8 0x00007fff FLREG9 0x00007fff FLREG10 0x00007fff FLREG11 0x00007fff FLREG12 0x00007fff FLREG13 0x00007fff FLREG14 0x00007fff FLREG15 0x00007fff

--- Details --- Region 0 (Descr. ) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00500000 - 0x01ffffff Region 2 (ME ) 0x00001000 - 0x004fffff Region 3 (GbE ) is unused. Region 4 (Platf. ) is unused. Region 5 (DevExp ) is unused. Region 6 (BIOS2 ) is unused. Region 7 (unknown) is unused. Region 8 (EC/BMC ) is unused. Region 9 (unknown) is unused. Region 10 (IE ) is unused. Region 11 (10GbE ) is unused. Region 12 (unknown) is unused. Region 13 (unknown) is unused. Region 14 (unknown) is unused. Region 15 (unknown) is unused.

=== Master Section === FLMSTR1 0x00200700 FLMSTR2 0x00400500

--- Details --- FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9 RegA RegB RegC RegD RegE RegF BIOS r rw r
ME r rw

Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Redrix". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 1 attached SPI flash chip with a density of 32768 kB. There is only one partition containing the whole address space (0x000000 - 0x1ffffff). There are 8192 erase blocks with 4096 B each. HSFC: FGO=1, FCYCLE=2, FDBC=2, SME=0 Chip identified: W25Q256JV_M Added layout entry 00000000 - 01ffffff named complete flash Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) on internal. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details).

This flash part has status UNTESTED for operations: WP The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 write_wp_bits: wp_verify reg:1 value:0x0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 write_wp_bits: wp_verify reg:1 value:0x0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 Reading ich descriptor... read_flash: Flash Descriptor region (00000000..0x000fff) is readable, reading range (00000000..0x000fff). Reading 4096 bytes starting at 0x000000. HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 HSFC: FGO=1, FCYCLE=0, FDBC=63, SME=0 done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 write_wp_bits: wp_verify reg:1 value:0x0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 write_wp_bits: wp_verify reg:1 value:0x0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 restore_power_management: Re-enabling power management. Using region: "bios". Error: Image size (8388608 B) doesn't match the expected size (33554432 B)! FAILED Restoring PCI config space for 00:1f:5 reg 0xdc

[MrChromebox]

REDRIX image files corrected/updated, please exit script and try again

[leenchan]

REDRIX image files corrected/updated, please exit script and try again

Downloading Full ROM firmware (coreboot_edk2-redrix-mrchromebox_20230615.rom)

Firmware download checksum fail; download corrupted, cannot flash.

i have try to download coreboot_edk2-redrix-mrchromebox_20230615.rom.sha1, but 404. missed updating sha1?

[MrChromebox]

sorry the checksum file didn't get uploaded, try again now plz

[leenchan]

sorry the checksum file didn't get uploaded, try again now plz

thank so much. bro. now successfully to flash. test full ROM now.