Sticky inputs in Bus converter DAC mode

Describe the bug The upper eight inputs of the bundled input of a bus converter are "sticky": the first falling edge on these wires after a chunk reload is ignored.

I looked into a bus converter's NBT data in-game, and had a poke around in the bus converter source code, and found what I think is the cause of the issue. Whether a wire on the bundled cable is non-zero or not is stored as a bit in bIn. While it seems to be defined in the Scala code as an Int (so the upper eight bits exist in the game logic), the bus converter's save and load functions treat it like a single byte. I think this is truncating the number and preventing the bus converter from detecting the first falling edge, as on a reload the converter thinks the upper inputs are already low.

Should be an easy fix (just store bIn as a larger type in NBT), though I'm not sure how tweaking how bIn is stored would affect pre-existing saves.

To Reproduce Steps to reproduce the behaviour:

Set up a bus converter in its DAC mode, so that the bundled side is an input.
Power the bundled side with one of upper eight wire colours (light grey to black)
Unload and reload the chunk (either by quitting and re-entering the world or moving far enough away to unload the chunk) a. Note: chunks near a world's spawnpoint are always loaded, so converters in spawn chunks only exhibit this behaviour on a quit/re-entry.
Turn off the bundled cable power, and you should observe the analogue output remain unchanged.

Expected behaviour The initial falling edges after a reload should always trigger an update.

Versions Include versions of the dependencies. And since you're looking at it, make sure ProjectRed is up to date. Don't submit bugs for old versions, as they could have been fixed.

CCL Version: 4.0.7.445
FMP Version: 3.0.4.123
MrTJPCore Version: N/A (in ProjectRed Core)
ProjectRed Version: 4.12.0

MrTJP / ProjectRed

Sticky inputs in Bus converter DAC mode #1758