Closed agostini01 closed 8 years ago
The implication of this behavior is fewer cycles by the end of the simulation. In memory intensive applications this may really decrease the number of cycles for the simulation if compared to its real hardware counterpart.
Hi Agostini01,
this issue is because in 5.0 is not checked that directory latency is 0. You could configure memory modules with DirectoryLatency = 1
from mem-config file for example . Although, you will see still a similar problem in "find_and_lock_event" when directory_entry is already locked, the issue will be solved for most acceses.
In m2s 4.2 by default directory_latency is 1 and it is checked that it is higher than 0 in src/mem_system/config.c. Do you simulate CPU or GPU?
"static struct mod_t mem_config_read_cache(struct config_t config, char *section){ ... if (dir_latency < 1) fatal("%s: cache %s: invalid value for variable " "'DirectoryLatency'.\n%s", mem_config_file_name, mod_name, mem_err_config_note); ..."
Do you simulate CPU or GPU?
I was simulating GPU, Southern Island Architecture with 4.2.
You could configure memory modules with DirectoryLatency = 1 from mem-config file for example.
I will take a look at this next week.
Additionally, what Next()
parameters configure? latency, dir_latency or other?
I have Latency assigned for global memory. Should I just assigned DirectoryLatency too?
; ---- Global memory
[Module si-gm]
Type = MainMemory
BlockSize = 64
Latency = 10
Additionally, what Next() parameters configure? latency, dir_latency or other?
Next() send the frame to the next event with the lantency that you indicate. As you can see depending on the event one latency is used or another. For example in System::EventLoadHandler (previously mod_handler_nmoesi_load()) Next() is used without latencies because some event can be processed in the same cycle.
I have Latency assigned for global memory. Should I just assigned DirectoryLatency
you should, this way you ensure that your directoryLatency is x and avoid problems like you mentioned in the first comment. In fact, do this:
As it is right now, I cannot run 5.0, to confirm it. I am not sure of the full implications but I believe changing: esim_engine->Next(frame) to esim_engine->Next(frame, 1) fixes the problem.
it is the same that esim_engine->Next(frame, directoryLatency) configuring DirectoryLatency = 1;
(for caches and main memory modules), and you will not need to program nothing.
Thank you, this was really enlightening. I will adopt this method next time.
I have been working in 4.2 and faced this issue. Which, after looking at Multi2Sim 5.0, I believe still persists.
Multiple memory port locks can happen on the same cycle (more them 2) because the locking and unlocking of ports does not take cycles to happen.
The issue happens due to the use of the function
esim_engine->Next(frame)
inModule.cc
file.Next()
'sint after
andint period
default to zero with its declaration inEngine.h
void Next(Event *event, int after = 0, int period = 0);
It would be great if someone could check if it persists in m2s 5.0. I run the simulation with:
--mem-debug debug.mem
Than I looked at this file:
cat debug.mem | grep -E "find and lock action" > find_and_lock_action.txt
This file shows it is possible to have more then 2 find and lock action within the same cycleAs it is right now, I cannot run 5.0, to confirm it. I am not sure of the full implications but I believe changing:
esim_engine->Next(frame)
toesim_engine->Next(frame, 1)
fixes the problem.