Open in-die-nibelungen opened 4 years ago
I'm sorry for the very long delay in my response.
As you mentioned, this error comes from Verilator, and I didn't run the entire simulation using Verilator in the ResNet18 and VGG-11 cases. So I couldn't find the this error in my side.
If there is any option to increase the array size in Verilator, we can run this simulation. Do anyone know how to increase the maximum array size in Verilator?
@shtaxxx ,
Thanks for your comment.
As you mentioned, this error comes from Verilator, and I didn't run the entire simulation using Verilator in the ResNet18 and VGG-11 cases. So I couldn't find the this error in my side.
I got it. The, are you using another simulator or not run simulation in these models? Another option is to reduce the memory size.
Do anyone know how to increase the maximum array size in Verilator?
I also would like to know how to specify this for Verilator if it exists.
Hello.
I'm very interested in inference on FPGA. Found nngen and trying out some examples.
cnn.py
andmlp.py
examples can be run without any problem, but an error, which isWidth of bit range is huge; vector of over 1billion bits: 0x40000000
, occured intorchvision_onnx_resnet18.py
.It seems like an error by verilator.My env is:
Is this example working on your side? I really appreciate it if you could tell me how to fix or where should I check to fix this.
Thanks.
Here is the full log by
torchvision_onnx_resnet18.py
: